Intel Corporation

Sean R Babcock

Orville H Christeson

Jerald N Hall

Frank E LeClerg

Frank L Wildgrube

Mike Kinion

John Yuratovac

Jay Joseph Nejedlo

Bruce Querbach

David G Ellis

Ananda G Sarangi

Eric S Gayles

Amjad M Khan

Eshwar Gollapudi

A built-in self test (IBIST) architecture/methodology is provided for testing the functionality of an interconnect (such as a bus) between two components. This IBIST architecture may include a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.

Testing methodology and apparatus for interconnects

A built-in self test (BIST) unit, of a primary integrated circuit (IC) component of a computer system, is programmed or hardwired with a test pattern. The test pattern is launched in multiple test cycles, to test an interconnect bus of the computer system or perform a device validation test of the component. A pin assignment of the pattern is automatically changed after each test cycle, without requiring re-programming of the BIST unit to do so.

Push button mode automatic pattern switching for interconnect built-in self test

A method and devices for a current dump circuit that includes a first termination device, a second termination device, and a current dump device. The first termination device resides outside the die of an IC. One end of the first termination device is operatively connected to a first voltage regulator. Another end of the first termination is device operatively connected to a signal line of the IC. The second termination device resides on a die of the IC. One end of the second termination device is operatively connected to a second voltage regulator. Another end of the second termination device is operatively connected to the signal line of the IC. The current dump device provides a path to remove any current flow between the first voltage regulator and the second voltage regulator.

Method and apparatus for balancing current in a system with two sets of termination devices

An apparatus includes a configuration selector that is selectively configurable to denote one of a plurality of operating modes for the apparatus, including a configuration mode. The apparatus further comprising a programmable multiplexer, a processor, a bus, and a storage medium having stored therein a basic input/output system (BIOS) equipped to operate in any one of the plurality of operating modes, including the configuration mode wherein the BIOS facilitates user programming of a plurality of operating parameters for the apparatus. The programmable multiplexer, responsive to the configuration selector, asserts a default bus/core ratio common to a plurality of processors and buses that can be employed to form the apparatus when the configuration selector is configured to denote the configuration mode of operation. The processor, coupled to the storage medium and the programmable multiplexer, operates to execute the BIOS, in a speed consistent with the asserted bus/core ratio. The bus, coupled to the programmable multiplexer, the processor and the storage medium, operates to provide instructions and data to the processor, including the BIOS, in a speed consistent with the asserted bus/core ratio.

Method and apparatus for setting the operating parameters of a computer system

An apparatus includes a storage medium having stored therein a segmented basic input/output system (BIOS) divided among a plurality of segments within the storage medium, and a processor operative to execute the segmented BIOS. In accordance with the teachings of the present invention, the BIOS includes a recovery function that is mode dependent in that while the apparatus is in an update mode the recovery function executes a full reflash of all relevant segments of the segmented BIOS, whereas while the apparatus is in a normal mode the recovery function executes a partial reflash of only identified corrupted BIOS segments.

Method and apparatus for updating a basic input/output system

A dual-in-line Universal Serial Bus (USB) connector including a plurality of USB ports, a plurality of signal pins associated with the ports, and a pair of mounting tabs. The USB connector is adapted for a circuit board including a first footprint for the dual-in-line USB connector situated at a predetermined location of the circuit board. Also, a second footprint is situated at a predetermined location of the circuit board for receipt of a different type of connector instead of the USB connector.

Dual-in-line universal serial bus connector

Method and apparatus for setting the operating parameters of a computer

A dual-in-line Universal Serial Bus connector including a plurality of Universal Serial Bus ports oriented adjacent to each other in a longitudinal direction. The dual-in-line Universal Serial Bus connector further includes a plurality of signal pins and a pair of mounting tabs. The signal pins are coupled to the plurality of Universal Serial Bus ports in order to receive data input into at least one of the plurality of Universal Serial Bus ports. The positioning of the mounting tabs and signal pins enable this connector to be used as a substitute for a serial communication (COM) port connector.

Dual-in line universal serial bus connector

A function of a computer other than a power supply function of the computer may also be controlled using a power control input of the computer. In response to a pressing of a power button or a closing of a power switch, a signal is provided which indicates that a function of the computer other than a power supply function of the computer may be performed. This may be implemented, for example, in response to the pressing of the power button or closing of the power switch for a time period longer than a predetermined time period. In response to a first condition at the power control input (for example, a momentary closing of the power switch or pressing of the power button), power is supplied to the computer. In response to a second condition at the power control input (for example, the closing of the power switch or pressing of the power button for a time period longer than a predetermined time period), a signal is provided indicating that a non-power supply function of the computer should be performed. For example, a basic input/output system (BIOS) program running on the computer performs an entering of a setup mode of the computer, a clearing, setting or a changing of the password, or a clearing of the system image of the computer in response to the pressing of the power button or closing of the power switch for a time period which is longer than a predetermined time period. Such an implementation does not require a user to open a system chassis of the computer and disconnect any configuration jumpers on the motherboard of the computer.

Control of a function of a computer other than a power supply function

An embodiment of the present invention provides a voltage comparator that senses the type of processor, unified or split voltage plane coupled to a mother board. Under the control of at least one multiplexer, voltage regulators supply voltage to the processor. If the processor is a unified voltage plane type, the voltage regulators are coupled together in a master/slave configuration to supply a single voltage to the processor. If the processor is a split voltage plane type, the voltage regulators are coupled to together in a master/master configuration where a core voltage regulator supplies a core voltage to the processor, and an I/O voltage regulator supplies an I/O voltage to the processor. This will allow each regulator to be set at a different voltages to accommodate processor types with different core and I/O voltages.

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Portland, OR, United States of America

Sean R Babcock