International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries Inc.

Sean David Burns

Sivananda K Kanakasabapathy

Matthew Earl Colburn

Lawrence Alfred Clevenger

Christopher J Penny

Nicole A Saulnier

Roger Allan Quon

Yann A M Mignot

Nelson M Felix

John Christopher Arnold

Dirk Pfeiffer

Yunpeng Yin

Steven J Holmes

Wu-Song S Huang

Dario Leonardo Goldfarb

David Robert Medeiros

Allen H Gabor

Chi-Chun Liu

Katherina E Babich

Scott David Halle

Arpan Pravin Mahorowala

Colin J Brodsky

Marie Angelopoulos

Daniel Sanders

Stuart A Sieg

Yongan Xu

Libor Vyklicky

Yann Alain Marcel Mignot

David V Horak

Michael Rizzolo

Marc Adam Bergendahl

Martin Burkhardt

Robert David Allen

Robert C Wong

Muthumanickam Sankarapandian

Kafai Lai

Richard Anthony Conti

Mahmoud M Khojasteh

Myung-Hee Na

Steven A Scheer

Habib Hichri

Jing Sha

Michael James Lercel

Anuja E DeSilva

Ryan L Burns

Jens Haetty

Mary Jane Brodsky

Wai-Kin Li

Ratnam Sooriyakumaran

Elbert Emin Huang

Albert Manhee Chu

Pushkara Rao Varanasi

Dongbing Shao

Phillip Joe Brock

Timothy A Brunner

Linda Karin Sundberg

Kuang-Jung Chen

Ankit Vora

Lin Zhou

Ryan O Jung

Kristin Schmidt

Bernhard R Liegl

Shahin Zangooie

Karen Temple

Michael M Crouse

Robert Allen David

Sudharshanan Raghunathan

Erin Catherine McLellan

Matt Pinnow

A method of forming a structure for etch masking that includes forming first dielectric spacers on sidewalls of a plurality of mandrel structures and forming non-mandrel structures in space between adjacent first dielectric spacers. Second dielectric spacers are formed on sidewalls of an etch mask having a window that exposes a connecting portion of a centralized first dielectric spacer. The connecting portion of the centralized first dielectric spacer is removed. The mandrel structures and non-mandrel structures are removed selectively to the first dielectric spacers to provide an etch mask. The connecting portion removed from the centralized first dielectric spacer provides an opening connecting a first trench corresponding to the mandrel structures and a second trench corresponding to the non-mandrel structures.

Self aligned pattern formation post spacer etchback in tight pitch configurations

A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.

Self-aligned pattern formation for a semiconductor device

A method for forming fins includes forming a three-color hardmask fin pattern on a fin base layer. The three-color hardmask fin pattern includes hardmask fins of three mutually selectively etchable compositions. Some of the fins of the first color are etched away with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind. The fins of the second color are etched away. Fins are etched into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

Alternating hardmasks for tight-pitch line formation

According to one or more embodiments of the present invention a computer-implemented method for fabricating a chip includes generating, using an aerial image generation system, a set of aerial images for a chip layout, the set of aerial images including an aerial image corresponding to each region from the chip layout. The method further includes automatically determining, using an artificial neural network, a feature vector for each aerial image from the set of aerial images. The method further includes clustering the aerial images using their corresponding feature vectors. The method further includes selecting, as test samples, a predetermined number of aerial images from each cluster. The method further includes performing a pattern coverage inspection of the chip layout using the aerial images that are selected as test samples.

Automatic feature extraction from aerial images for test pattern sampling and pattern coverage inspection for lithography

Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

Selective gas etching for self-aligned pattern transfer

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a &#x3b2; line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a &#x3b3; line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an &#x3b1; line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a &#x3b2;&#x3b3;&#x3b2; jog; a &#x3b2;&#x3b1;&#x3b2; jog; an &#x3b1;&#x3b2;&#x3b3; jog; a &#x3b3;&#x3b2;&#x3b1; jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs

A technique relates to a circuit. At least one 4 transistor (4T) static random access memory (SRAM) bitcell is included. Each of the 4T SRAM bitcells includes a first PFET, a first NFET, a second PFET, and a second NFET, the first PFET and the first NFET being coupled to form a first output node, and the second PFET and the second NFET being coupled to form a second output node. A pulldown circuit is coupled to the first NFET, the pulldown circuit operable to pull down a voltage at the first output node. A feedback circuit is operable to monitor the first output node, the feedback circuit operable to control the pulldown circuit.

4T static random access memory bitcell retention

Lithographic patterning methods are provided which implement directed self-assembly (DSA) of block copolymers to enable self-aligned cutting of features. A first layer and second layer of material are formed on a substrate. The second layer of material is lithographically patterning to form a guiding pattern. A DSA process is performed to form a block copolymer pattern around the guiding pattern, which comprises a repeating block chain that includes at least a first block material and a second block material, which have etch selectivity with respect to each other. A selective etch process is performed to selectively etching one of the first block material and the second block material to form self-aligned openings in the block copolymer pattern which expose portions of the first layer of material. The first layer of material is patterned by etching the exposed portions of the first layer of material.

Self-aligned patterning methods which implement directed self-assembly

An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure includes three types of lines: a &#x3b2; line defined by a patterned bottom mandrel formed in the self-aligned quadruple patterning process; a &#x3b3; line defined by location underneath a top mandrel formed in the self-aligned quadruple patterning process; and an &#x3b1; line defined by elimination located underneath neither the top mandrel or the bottom mandrel formed in the self-aligned quadruple patterning process. The interconnect structure further includes multi-track jogs selected from a group consisting of a &#x3b2;&#x3b3;&#x3b2; jog; a &#x3b2;&#x3b1;&#x3b2; jog; and &#x3b1;&#x3b2;&#x3b3; jog; a &#x3b3;&#x3b2;&#x3b1; jog, and combinations thereof. The first and third positions refer to the uncut line and the second position refers to the cut line in the self-aligned quadruple patterning process.

A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of patterned structures. The method also includes training, utilizing physical design layout patterns containing hotspots, a first neural network model configured to generate synthetic physical design layout patterns, and training, utilizing physical design layout patterns that do and do not contain hotspots, a second neural network model configured to classify whether physical design layout patterns contain hotspots. The method further includes generating synthetic physical design layout patterns containing hotspots by utilizing the trained first neural network model to generate synthetic physical design layout patterns and utilizing the trained second neural network model to select the synthetic physical design layout patterns containing hotspots. The method further includes evaluating manufacturability of a given patterned structure comprising at least one of the synthetic physical design layout patterns containing at least one hotspot.

Generation of hotspot-containing physical design layout patterns

Growing community of inventors

Armonk, NY, United States of America

Sean David Burns