Skhynix Inc.

Hynix Semiconductor Inc.

Se Ho Lee

Hyangkeun Yoo

Jae Gil Lee

Hae Chan Park

Jae Hyun Han

Myoung Sub Kim

Seung Yun Lee

Ju Ry Song

Min Gu Kang

Dong Ik Suh

Bo Yun Kim

Soo Gil Kim

Won Tae Koo

Jung Won Seo

Sang Chul Oh

Sung Bin Hong

A memory system includes a non-volatile memory device and a performance manager. The performance manager activates a plurality of sub-controllers according to a setting of a host device, allocates memory regions respectively to the plurality of sub-controllers, the memory regions being included in the non-volatile memory device, and determines, according to maximum performance values and a size ratio of the memory regions, credit sets to be allocated respectively to the plurality of sub-controllers.

Memory system and operating method of the memory system

A nonvolatile memory device includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

Nonvolatile memory device having a ferroelectric layer

A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed on the substrate, a gate electrode layers disposed on the resistance change layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed in the substrate and contact different portions of the resistance change layer. The resistance change layer includes movable oxygen vacancies or movable metal ions.

Nonvolatile memory device having resistance change layer

A semiconductor device according to an embodiment of the present disclosure includes a substrate, a gate structure disposed over the substrate, a dielectric structure disposed to contact a sidewall surface of the gate structure over the substrate, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. The gate structure includes a gate electrode layer and an interlayer insulation structure which are alternately stacked. The interlayer insulation structure includes a metal-organic framework layer.

Semiconductor device including interlayer insulation structure including metal-organic framework

Disclosed are a controller that controls a memory device, and an operating method of the controller. The controller may include a host interface suitable for fetching a write command received from a host; and a processor suitable for controlling a write operation of the memory device in response to the fetched write command, wherein, when a workload of a background operation of the processor is greater than a workload of a host write operation, the host interface is further suitable for: determining a delay amount of time and providing the host with a completion response to the write command after delaying the completion response by the delay amount of time.

Controller and operating method thereof

A nonvolatile memory device according to an embodiment includes a substrate, a channel structure extending in a direction perpendicular to the substrate; a charge storage structure disposed to be in contact with the channel structure; and a cell electrode structure disposed to be in contact with the charge storage structure in a lateral direction, wherein the channel structure comprises a hole conduction layer and an electron conduction layer.

Nonvolatile memory device having multiple numbers of channel layers

A semiconductor device is provided. The semiconductor device includes a substrate, an electrode stack disposed on the substrate, the electrode stack including an interlayer insulation layer and a gate electrode structure that are alternately stacked in a direction perpendicular to the substrate, a trench penetrating the electrode stack to expose sidewall surfaces of the interlayer insulation layer and the gate electrode structure, a gate dielectric layer disposed along a sidewall surface of the trench, the gate dielectric layer including a ferroelectric portion and a non-ferroelectric portion, and a channel layer disposed to adjacent to the gate dielectric layer. The ferroelectric portion is in contact with the gate electrode structure, and the non-ferroelectric portion is in contact with the interlayer insulation layer.

Semiconductor device having ferroelectric material and method of fabricating the same

A nonvolatile memory device according to an aspect of the present disclosure includes a substrate having a channel layer, a gate dielectric layer structure disposed on the channel layer, a ferroelectric layer disposed on the gate dielectric layer structure, and a gate electrode layer disposed on the ferroelectric layer. The gate dielectric layer structure has a positive capacitance. The ferroelectric layer has a negative capacitance. The gate dielectric layer structure includes a charge tunneling layer, a charge trap layer and a charge barrier layer disposed on the channel layer.

Nonvolatile memory device including ferroelectric layer having negative capacitance

A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.

A semiconductor device according to an embodiment includes a substrate, a bit line structure and a source line structure respectively extending in a direction perpendicular to a surface of the substrate, a semiconductor layer disposed between the bit line structure and the source line structure on a plane parallel to the surface of the substrate, a first ferroelectric layer disposed on a first surface of the semiconductor layer, and a first gate electrode layer disposed on the first ferroelectric layer.

Semiconductor device including ferroelectric layer and method of manufacturing the same

In a method of fabricating a nonvolatile memory device according an embodiment, a first tunnel oxide layer, a nitrogen supply layer, and a second tunnel oxide layer having a density lower than that of the first tunnel oxide layer are formed on a substrate. Nitrogen in the nitrogen supply layer is diffused into the second tunnel oxide layer to convert at least a portion of the second tunnel oxide layer into an oxynitride layer.

Method of diffusing nitrogen into a tunnel layer of a nonvolatile memory

A semiconductor device may include: a first electrode; a second electrode; and a multilayer stack that is interposed between the first electrode and the second electrode and includes a seed layer and a high-k dielectric layer, wherein each of the seed layer and the high-k dielectric layer may have a rocksalt crystal structure, and wherein the high-k dielectric layer may exhibit a dielectric constant (k) of fifty (50) or higher.

Semiconductor device including multilayer stack including seed layer and high-k dielectric layer

A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed over the substrate, a gate insulation layer disposed on the resistance change layer, a gate electrode layer disposed on the gate insulation layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed respectively over the substrate and disposed to contact a different portion of the resistance change layer.

Nonvolatile memory device having a resistance change layer and a plurality of electrode pattern layers

A nonvolatile memory device according to an embodiment includes a substrate, a gate electrode structure disposed on the substrate, a gate dielectric layer covering at least a portion of a sidewall surface of the gate electrode structure on the substrate, a channel layer and a resistance change structure that are sequentially disposed on the gate dielectric layer, and a plurality of bit line structures disposed inside the resistance change structure.

Nonvolatile memory device having resistance change memory layer

A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

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Gyeonggi-do, South Korea

Se Ho Lee