Samsung Electronics Co., Ltd.

Soulbrain Co., Ltd.

Se-Ho Cha

Kyunghyun Kim

Daehong Eom

Jun-Youl Yang

Hoon Hee Han

Yongsun Ko

ChangSup Mun

Kyounghwan Kim

Jihoon Jeong

Sang Won Bae

Jinuk Lee

Kwangsu Kim

Jaewan Park

Junghun Lim

Seonghwan Park

Byoungmoon Yoon

Chanjin Jeong

Yanghwa Lee

Kihyun Hwang

JinGyun Kim

Daehyun Jang

Sunghae Lee

Chadong Yeo

Young-taek Hong

Seongsoo Lee

Jinwoo Lee

Byoung-Moon Yoon

Dae-Hyuk Chung

Keonyoung Kim

Dae-Keun Kang

Kyung-hyun Kim

Young Taek Hong

Dae-hong Eom

Choongkee Seong

Sunjoong Song

Disclosed are a method of wet etching and a method of fabricating a semiconductor device. The wet etching method includes providing a wafer in a process bath and an etchant is accommodated, supplying the process bath with a primary etchant to control a concentration of a specific material in the etchant, supplying the process bath with a first additive to increase the concentration of the specific material in the etchant, and supplying the process bath with a second additive to suppress a defect caused by an increase in the concentration of the specific material in the etchant. The etchant includes at least one, of the primary etchant, the first additive, and the second additive. The first additive and the second additive are separately supplied to the process bath.

Method of wet etching and method of fabricating semiconductor device using the same

Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.

Methods of fabricating three-dimensional semiconductor devices

Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound material. The silicon compound material includes a silicon atom, at least one selected from the group of a nitrogen atom, a phosphorus atom and a sulfur atom combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

Compositions for etching

Etching compositions are provided. The etching composition includes a phosphoric acid, ammonium ions and a silicon compound. The silicon compound includes a silicon atom, an atomic group having an amino group combined with the silicon atom, and at least two oxygen atoms combined with the silicon atom. Methods utilizing the etching compositions are also provided.

Compositions for etching and methods of forming a semiconductor device using the same

Three dimensional semiconductor memory devices and methods of fabricating the same

According to an example embodiment, a non-volatile memory device includes a semiconductor layer pattern on a substrate, a plurality of gate patterns and a plurality of interlayer insulating layer patterns that are alternately stacked along a side wall of the semiconductor layer pattern, and a storage structure between the plurality of gate patterns and the semiconductor layer pattern. The semiconductor layer pattern extends in a vertical direction from the substrate. The gate patterns are recessed in a direction from a side wall of the interlayer insulating layer patterns opposing the side wall of the semiconductor layer pattern. A recessed surface of the gate patterns may be formed to be vertical to a surface of the substrate.

Non-volatile memory device having vertical structure and method of manufacturing the same

A mold stack including alternating insulation layers and sacrificial layers is formed on a substrate. Vertical channel regions extending through the insulation layers and sacrificial layers of the mold stack are formed. Gate electrodes are formed between adjacent ones of the insulation layers and surrounding the vertical channel regions. The gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location further away from the sidewalls of the insulation layers.

Vertical channel memory devices with nonuniform gate electrodes and methods of fabricating the same

Vertical channel memory devices with nonuniform gate electrodes

Example embodiments of the present invention relate to methods of treating and removing a photoresist pattern and a method of manufacturing a semiconductor device using the same. Other example embodiments of the present invention relate to a method of treating a photoresist pattern and a method of removing a photoresist pattern formed using a photoresist composition suitable for argon fluoride (ArF). In a method of removing a photoresist pattern, an ozone vapor including a water vapor and an ozone gas may be provided onto the photoresist pattern to remove a hydrophobic group from a photoresist resin included in the photoresist pattern. A cleaning solution may be provided to make the photoresist pattern water-soluble. A cleaning process may be performed on the photoresist pattern to remove the photoresist pattern. The photoresist pattern may be effectively removed without an increased processing time and/or damage to a substrate.

Method of treating and removing a photoresist pattern and method of manufacturing a semiconductor device using the same

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Goyang-si, South Korea

Se-Ho Cha