International Business Machines Corporation

Scott Preston Moore

James Warren Wilson

John Steven Kresge

Natalie Barbara Feilchenfeld

Ronald P Nowak

Stephen R Engle

Robin A Susko

Stephen Wesley MacQuarrie

Mukund Kantilal Saraiya

John Andrew Shriver, Iii

Lance A Bronson

An electronic package device is disclosed including a microelectronic package and a heat sink positioned over the microelectronic package. A thermal interface element is positioned between the microelectronic package and the heat sink. The thermal interface element is elongated and has differing thicknesses along its length to enhance the dissipation of heat.

Optimization of electronic package geometry for thermal dissipation

The present invention provides an organic chip carrier particularly useful with flip chips. The chip carrier comprises an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry. The fine line circuitry has a line width of about 2.0 mil or less, preferably about 1.0 mil or less, and more preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.

Polytetrafluoroethylene thin film chip carrier

An assembly and process for connecting opposed semiconductor structures (12,14) comprising at least two structures. An interconnect (16) between the structures (12,14) connects the structures in opposed spaced relation to each other. The interconnect comprises a first material (18) and a second material (20). The first material comprises a resiliently flexible center portion. The second material comprises an electrically conductive outer portion surrounding the first material. The second material and the first material provide the interconnect with a flexibly compliant characteristic for maintaining an electrically conductive relationship between the structures.

Semiconductor structure interconnector and assembly

The present invention provides an organic chip carrier particularly useful with flip chips, comprising an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry having line width of about 2.0 mil or less, preferably about 1.0 mil or less, preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less, disposed on the conformational layer. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 30%. The invention also relates to methods of making the dielectric coated chip carrier.

The present invention provides an organic chip carrier particularly useful with flip chips, comprising an organic dielectric layer, a first layer of circuitry disposed on the dielectric layer, an organic conformational coating disposed over the first layer of dielectric and the first layer of circuitry, and a layer of fine line circuitry having line width of about 2.0 mil or less, preferably about 1.0 mil or less, preferably about 0.7 mil, and a space between lines of about 1.5 mil or less, preferably about 1.1 mil or less, disposed on the conformational layer. Preferably the dielectric layer is free of woven fiber glass. The conformational coating preferably has a dielectric constant of about 1.5 to about 3.5, and a percent planarization of greater than about 3.5% The invention also relates to methods of making the dielectric coated chip carrier.

A thermally enhanced ball grid array package for electronic components, with an electronic and a plurality of ceramic component carriers bonded to a metal heat sink, enhances thermal performance, reduces solder ball fatigue and reduces stresses between the ceramic component carriers and the heat sink. Bonding the ceramic component carriers to the heat sink reduces expansion induced stresses of the solder balls on the carriers. Plural ceramic component carriers, smaller than a single carrier would have to be for the same package, reduce stresses at the interfaces between the ceramic component carriers and the heat sink.

Thermally enhanced ball grid array package

A ceramic chip carrier is disclosed which preferably includes a ceramic substrate having a circuitized surface, at least one semiconductor chip mounted on the circuitized surface, and at least one pin which is mechanically and electrically connected to a contact pad on the circuitized surface. Each mechanical/electrical connection between a pin and a contact pad includes a conventional solder connection. In addition, each such solder connection is at least partially encapsulated in a material, including an epoxy resin, which is chosen in relation to the solder connection to enable the solder connection to withstand a standard thermal fatigue test.

Pinned ceramic chip carrier

A ceramic chip carrier is disclosed which includes a ceramic substrate having a circuitized surface, at least one semiconductor chip mounted on the circuitized surface, and a lead frame or edge clip which is mechanically and electrically connected to contact pads on the circuitized surface. Each mechanical/electrical connection between the lead frame or edge clip and the contact pads includes a conventional solder connection. In addition, each such solder connection is at least partially encapsulated in a material, including an epoxy resin, which is chosen in relation to the solder connection to enable the solder connection to withstand a standard thermal fatigue test.

Growing community of inventors

Apalachin, NY, United States of America

Scott Preston Moore