International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies Ag

Other

Infineon Technologies North America Corp.

Scott Marshall Mansfield

Lars W Liebmann

Ioana C Graur

Geng Han

Maharaj Mukherjee

James A Culp

Alfred K Wong

Henning Haffner

Zachary Baum

Alan Edward Rosenbluth

Kafai Lai

Derren Neylon Dunn

Richard A Ferguson

Azalia A Krasnoperova

Ramya Viswanathan

Jason E Meiring

David Clifford Long

Matthew Earl Colburn

Mark Alan Lavin

Yunpeng Yin

Steven Alan Cordes

Stuart A Sieg

Mark J LaPlante

Christopher P Ausschnitt

Timothy A Brunner

James L Speidell

Amith Singhee

Ulrich Alfons Finkler

Scott David Halle

Ashok Pon Kumar Sree Prakash

Allen H Gabor

Haoren Zhuang

James Allan Bruce

David Osmond Melville

Shahid Ahmad Butt

Daniel James Dechene

Michael E Scaman

Donald J Samuels

Dario Gil

Helen Wang

Michael James Cordes

Klaus Herold

David S O'Grady

Gregory J Dick

Steven N Hirsch

Mark O Neisser

Yuping Cui

Dominique L Nguyen-Ngoc

Christopher Douglas Wait

Mark R King

Mohamed Talbi

Alfred Kwok-Kit Wong

William Harry Vonderhaar

Zengqin Zhao

A method of presenting data over a Web service interface includes: establishing, by a first computer process, a persistent transmission control protocol (TCP) network connection between the first computer process and a second computer process; dynamically allocating, by the second computer process, memory in response to receipt of static data over the persistent TCP network connection from the first computer process; updating, by the second computer process, the memory in response to receipt of dynamic data received over the persistent TCP network connection from the first computer process; and enabling, by the second computer process, a Web server to access the updated data for presentation by the Web service interface. The static data identifies a given entity and the dynamic data includes metric data provided for the entity.

Unifying realtime and static data for presenting over a web service

A method of mask correction where two independent process models are analyzed and co-optimized simultaneously. In the method, a first lithographic process model simulation is run on a computer system that results in generating a first mask size in a first process window. Simultaneously, a second hard mask open etch process model simulation is run resulting in generating a second mask size in a second process window. Each first lithographic process model and second hard mask open etch process model simulations are analyzed in a single iterative loop and a common process window (PW) optimized between lithography and etch is obtained such that said first mask size and second mask size are centered between said common PW. Further, an etch model form is generated that accounts for differences in an etched pattern due to variation in three-dimensional photoresist profile, the model form including both optical and density terms that directly relate to an optical image.

Method of simultaneous lithography and etch correction flow

In an approach for predicting a process fail limit for a semiconductor manufacturing process, a computer determines a potential working process condition for each of a plurality of process parameters varied in forming a test wafer feature. The computer determines a process sigma value for each of the plurality of process parameters in forming the test wafer feature and a measurement sigma value. The computer evaluates a set of measurements of the test wafer feature compared to an acceptable wafer feature dimension, where each measurement of the set of measurements is a pass or fail as compared to the acceptable wafer feature dimension. The computer determines whether one or more fails are evaluated compared to the acceptable wafer feature dimension. The computer produces a predicted process fail limit based, at least in part, on the evaluation of fails, the measurement sigma value, and a desired target sigma value.

Predicting process fail limits

A method of fabricating a semiconductor device includes forming a masking layer on an upper surface of a semiconductor substrate. The masking layer is patterned to form at least one masking element that designates an active region of the semiconductor substrate and at least one patterning assist feature adjacent the at least one masking element. An etching process is performed to form a plurality of semiconductor fins on the semiconductor substrate. The plurality of semiconductor fins include at least one isolated fin formed on the active region according to the at least one masking element and at least one sacrificial fin formed according to the patterning assist feature that reduces a loading effect that occurs during the etching process.

Patterning assist feature to mitigate reactive ion etch microloading effect

Improved fidelity to an integrated circuit pattern design in a semiconductor structure ultimately produced is achieved by modeling material removal and deposition processes in regard to materials, reactant, feature size, feature density, process parameters and the like as well as the effects of such parameters on etch and material deposition bias due to microloading and RIE lag (including inverse RIE lag) and using the models to work backward through the intended manufacturing method steps, including hard mask pattern decomposition, to morphologically develop feature patterns for use in most or all process steps which will result in the desired feature sizes and shapes at the completion of the overall process. Modeling of processes may be simplified through use of process assist features to locally adjust rates of material deposition and removal.

Pattern improvement in multiprocess patterning

Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes.

Decomposition with multiple exposures in a process window based OPC flow using tolerance bands

Aspects of the invention include a computer-implemented method of designing a photomask. In one embodiment, the method comprises: simulating a first photomask patterning process using a first photomask design to create simulated contours; comparing the simulated contours to a desired design; identifying regions not common to the simulated contours and the desired design; creating desired target shapes for a second photomask patterning process subsequent to the first photomask patterning process based upon the identified regions; and providing the desired target shapes for forming of a second photomask design based upon the desired target shapes.

Generating cut mask for double-patterning process

A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.

Multilayer OPC for design aware manufacturing

A method is provided for calibrating a model of a lithographic process that includes defining a parameter space of lithographic model parameters that are expected in an integrated circuit layout. The parameter space is defined according to bin values of a lithographic model parameter that span the range from a predetermined minimum and maximum value of the model parameter. The bin values may be incremented uniformly between the maximum and minimum parameter values, or may be distributed according to a weighting. The lithographic model is calibrated to an initial calibration test pattern. The resulting simulated calibration pattern is evaluated to determine whether the model parameter space is adequately populated. If the parameter space is over or under populated, the calibration pattern is modified until the calibration pattern test values adequately populate the parameter space, so that the final calibrated lithographic process model will more reliably predict images over the full range of image parameters.

Calibration of lithographic process models

Solutions for verifying photomask designs are disclosed. In one embodiment, a method of verifying a photomask design includes: simulating an initial semiconductor manufacturing process using a plurality of mask shapes and variation models for the initial semiconductor manufacturing process, to generate a plurality of contours for the initial semiconductor manufacturing process; simulating a subsequent semiconductor manufacturing process using the contours for the initial semiconductor manufacturing process and variation models for the subsequent semiconductor manufacturing process, to generate a plurality of contours for the subsequent semiconductor manufacturing process; repeatedly simulating at least one further subsequent semiconductor manufacturing process using a plurality of contours for the subsequent semiconductor manufacturing process and variation models for the further subsequent semiconductor manufacturing process; and generating and storing a verification result for the photomask design on a computer readable storage medium.

Photomask design verification

A method is provided for modeling lithographic processes in the design of photomasks for the manufacture of semiconductor integrated circuits, and more particularly for simulating intermediate range flare effects. For a region of influence (ROI) from first ROIof about 5&#x3bb;/NA to distance ROIwhen the point spread function has a slope that is slowly varying according to a predetermined criterion, then mask shapes at least within the distance range from ROIto ROIare smoothed prior to computing the SOCS convolutions. The method provides a fast method for simulating intermediate range flare effects with sufficient accuracy.

Fast and accurate method to simulate intermediate range flare effects

Embodiments of the present invention provide a method of performing photo-mask correction. The method includes identifying a hot-spot in a photo-mask that violates one or more predefined rules; creating a window area in the photo-mask that surrounds the hot spot; categorizing the window area; selecting a solution, from a library of pre-computed solutions, based on a category of the window area; and applying the solution to the hot spot. A service-oriented architecture (SOA) system that synchronizes the design to the process is also provided.

Short path customized mask correction

Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes depositing a gate material over a semiconductor substrate, and depositing a first resist layer over the gate material. A first mask is used to pattern the first resist layer to form first and second resist features. The first resist features include pattern for gate lines of the semiconductor device and the second resist features include printing assist features. A second mask is used to form a resist template; the second mask removes the second resist features.

Integrated circuits and methods of design and manufacture thereof

A method for generating a mask pattern is provided. A target lithographic pattern comprising a plurality of first geometric regions is provided, wherein the regions between the plurality of first geometric regions comprise first spaces. The target lithographic pattern is transformed, and the transformed pattern is decomposed into a first pattern and a second pattern.

Mask and method for patterning a semiconductor wafer

Growing community of inventors

Hopewell Junction, NY, United States of America

Scott Marshall Mansfield