International Business Machines Corporation

Northern Telecom Limited

Mcnc

Mosaic, Ltd

Polylithics, Inc.

Scott L Jacobs

Perwaiz Nihal

Burhan Ozmat

Henri D Schnurmann

Jane M Shaw

Arthur R Zingher

Michael Hatzakis

Edward D Babich

David F Witman

Juri R Parasczcak

William R Brunsvold

Willard E Conley

Arnold Reisman

Giora Dishon

Iwona Turlik

Maurice T McMahon

Neil M Poley

David Paul Merritt

George L Mack

Deepak Nayak

Lih-Tyng Hwang

Robert F Darveaux

Ann M Uptmor

A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.

High performance integrated circuit chip package

A low cost, lightweight, fast, dense and reliable extended integration semiconductor structure is provided by forming a thin film multilayer wiring decal on a support substrate and aligning and attaching one or more integrated chips to the decal. A support ring is attached to the decal surrounding the aligned and attached integrated substrate, and the support substrate is removed. Reach-through vias connect the decal wiring to the chips.

Method of making a extended integration semiconductor structure

Extended integration semiconductor structure with wiring layers

Plasma-resistant polymeric materials are prepared by reacting a polymeric material containing reactive hydrogen functional groups with a multifunctional organometallic material containing at least two functional groups which are reactive with the reactive hydrogen functional groups of the polymeric material, such as hexamethylcyclotrisilazane.

Plasma-resistant polymeric material, preparation thereof, and use thereof

An integrated circuit chip packaging structure, preferably having a semiconductor base substrate, i.e., silicon or gallium arsenide, alternating insulation and conductive layers on the base structure, at least two conductive layers being patterned into thin film wiring (i.e., thin film copper of approximately 5 microns), semiconductor integrated circuit chips connected to the upper-most patterned conductive layer, and means to connected the packaging structure to the next level of packaging (i.e., board or card). The thin film wiring layers typically each having coplanar ground, power and signal lines, with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate efficient power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes to form three dimensional power planes. To reduce package capacitance and keep the RC constant low, a personalized reference plane is incorporated. The personalized plane has insulating regions extending at least partially through the plane at predetermined locations that coincide with long signal lines on the wiring layers. The combined package provides a packaging alternative that has excellent electrical performance (i.e., speed, low RC constant, efficient power distribution), high density and thermal expansion matching between the underlying semiconductor structure and semiconductor chips mounted on the package. A high yield process for manufacturing the package is also disclosed.

Module for packaging semiconductor integrated circuit chips on a base

A composition for use in a process for the deposition of patterned thin metal films on integrated circuit substrates, the composition comprising an admixture of a thermoplastic polyimide resin and a coumarin dye dissolved in a substituted phenol solvent. Optionally a polar solvent having a boiling point greater than 160.degree. C. and a low boiling organic compound (70.degree.-150.degree. C.) may be incorporated in the composition.

Polyimide formulation for forming a patterned film on a substrate

A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a 'good machine' simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site. The combination of partitioning along chip boundaries, simple and inexpensive testing without external testers or mainframe computers, and enhanced diagnostics are made possible by the present invention.

Method of partitioning, testing and diagnosing a VLSI multichip package

A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures are combined by decals to form a central processing unit of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments.

High performance integrated circuit packaging structure

Growing community of inventors

Apex, NC, United States of America

Scott L Jacobs