Texas Instruments Corporation

Scott H Prengle

Robert H Eklund

James Carl Baker

Robert Kraft

Henry W Trombley

A five step, low pressure, high-density-plasma etch process used to etch complicated DRAM transistor gate stacks with high inter-layer selectivity. Such stacks typically consist of the following layers: silicon nitride ( ), tungsten ( ), titanium nitride ( ), and polysilicon ( ). The process includes one step for each of the four layers in the gate stack, and one step to ash the photoresist. These five process steps can preferably be performed in four separate chambers on a cluster tool platform. The innovative etch process of the present invention fabricates gates with lengths of 0.25 microns and below with excellent profile, excellent linewidth uniformity across the wafer, and minimal loss of the gate oxide.

Gate stack and etch process

A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors. Subsequent patterning and etching of the polysilicon, followed by sidewall filament formation and source/drain doping, is performed to complete the structure.

Integrated circuit structure having a bipolar transistor with a thick base oxide and a field effect transistor with a thin gate oxide

Method for forming a thick base oxide in a BiCMOS process

A method for fabricating a DMD spatial light modulator (10, 66) using an aluminum hard mask (40,50,80,90). The DMD superstructure (14,16) is comprised entirely of titanium tungsten (TiW), whereby the hinge (14) and beam (16) are patterned by a respective thin aluminum hard mask. A very rigid superstructure (14,16) is achieved, and the use of a sacrificial oxide hard mask is avoided. With the thin aluminum hard mask (40,80), good step coverage of subsequent layers is achieved. Relatively few semiconductor processing steps are required, with the titanium tungsten layers (32,44,72,84) being etched away with a fluorinated plasma. In one embodiment, the photoresist spacer layer (30) is never exposed to a fluorinated plasma.

Method for creating a digital micromirror device using an aluminum hard

A method of fabricating micro-mechanical devices that use support elements (13) raised from a substrate (15), to support moveable elements (11). First, support elements (13) having reflective top surfaces (31) are fabricated. A layer of photoresist material (41) is then deposited over the support elements (13), to a thickness that substantially covers their reflective top surfaces (31). The photoresist layer (41) is exposed, which results in the areas (61) over the support elements (13) being more highly exposed than the areas (62) between the support elements (13). This permits a subsequent developing step that can be controlled to the purpose of removing the photoresist between the support elements (13) to a height planar with the reflective top surfaces of the support elements, while guaranteeing that the photoresist will be removed over the support elements (13).

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Plano, TX, United States of America

Scott H Prengle