Advanced Micro Devices Corporation

Texas Instruments Corporation

Scott Gregory Bushman

Thomas J Sonderman

William Jarrett Campbell

Edward Christopher Stewart

Anthony John Toprac

Haowen Bu

Elfido Coss, Jr

Michael Lee Miller

Matthew A Purdy

Douglas J Bonser

Craig William Christian

Periannan Chidambaram

Richard David Edwards

James H Hussey, Jr

Curtis Warren Doss

Anastasia Lynn Oshelski Peterson

Exemplary embodiments provide methods for implementing an ultra-high temperature (UHT) anneal on silicon germanium (SiGe) semiconductor materials by co-implanting carbon into the SiGe material prior to the UHT anneal. Specifically, the carbon implantation can be employed to increase the melting point of the SiGe material such that an ultra high temperature can be used for the subsequent anneal process. Wafer warpage can then be reduced during the UHT anneal process and potential lithographic mis-alignment for subsequent processes can be reduced. Exemplary embodiments further provide an inline control method, wherein the wafer warpage can be measured to determine the litho-mis-alignment and thus to control the fabrication process. In various embodiments, the disclosed methods can be employed for the fabrication of source/drain extension regions and/or source/drain regions of transistor devices, and/or for the fabrication of base regions of bipolar transistors.

Methodology of implementing ultra high temperature (UHT) anneal in fabricating devices that contain sige

A method is provided, the method comprising monitoring consumption of a sputter target to determine a deposition rate of a metal layer during metal deposition processing using the sputter target, and modeling a dependence of the deposition rate on at least one of deposition plasma power and deposition time. The method also comprises applying the deposition rate model to modify the metal deposition processing to form the metal layer to have a desired thickness.

Run-to-run control method for automated control of metal deposition processes

A method and apparatus for controlling wafer thickness uniformity in a multi-zone vertical furnace is provided. The multi-zone furnace bakes a plurality of wafers within each zone for a first bake time. A film thickness of at least one wafer baked in each zone of the furnace is measured using a metrology tool. A film thickness optimization unit determines a deposition rate for the at least one wafer within each zone, with the deposition rate being determined as a function of the film thickness of the wafer and the first bake time. The film thickness optimization unit then determines a second bake time to bake a subsequent set of wafers, and the subsequent set of wafers is baked in the furnace for the second bake time.

Method and apparatus for controlling wafer thickness uniformity in a multi-zone vertical furnace

The present invention is directed to a method of controlling an etching process used to form a gate electrode on a semiconductor device. In one embodiment, the method comprises forming a layer of silicon dioxide above a semiconducting substrate, and forming a layer of polysilicon above the layer of silicon dioxide. The method further comprises sensing a thickness of the layer of polysilicon and adjusting, based upon the sensed thickness of said layer of polysilicon, at least one parameter of an etching process to be performed on said layer of polysilicon to define a gate electrode of a transistor, said etching process comprised of at least a timed etch process and an endpoint etch process.

Control of two-step gate etch process

In one illustrative embodiment, a method is provided that controls a stepper to position a focal plane of a light source adjacent a top surface of a layer of photoresist. A metrology tool is used to measure a thickness of the layer of photoresist, and a controller uses the thickness measurement to determine a position of the top surface of the layer of photoresist. The controller delivers a control signal to the stepper, causing the stepper to move the focal plane of the light source adjacent the top surface of the layer of photoresist.

Method and apparatus for controlling focus based on a thickness of a layer of photoresist

A method comprising determining a polishing profile produced by a polishing tool and manufacturing a process layer with a surface profile prior to polishing operations based upon the determined polishing profile of the polishing tool.

Method for adjusting incoming film thickness uniformity such that variations across the film after polishing minimized

A method and apparatus for integrating tool sensor data in an Advanced Process Control (APC) application. A sensor receives operational state data of a processing tool related to the manufacture of a processing piece. The state data is sent from the sensor to a data server and accumulated therein. The data server processes the state data and forwards the data to an APC framework. The APC framework then forwards the state data to a fault detection unit. The fault detection unit determines if a fault condition exists with the processing tool based upon the state data. A predetermined action is performed on the processing tool in response to the presence of a fault condition. In accordance with one embodiment, the predetermined action is to shutdown the processing tool so as to prevent further production of faulty wafers.

Method and apparatus for the integration of sensor data from a process tool in an advanced process control (APC) framework

In one illustrative embodiment, a system is provided for controlling a lens of an optical system of a stepper. The system comprises the stepper, the optical system, and a controller. The stepper has a light source controllably energizable to provide light to a surface of a semiconductor device. The lens of the optical system has a controllable focus. The controller is capable of determining a temperature of the lens, and controllably varying the focus of the lens in response to the temperature of the lens.

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Richardson, TX, United States of America

Scott Gregory Bushman