Texas Instruments Corporation

Scott G Balster

Jeffrey A Babcock

Angelo Pinto

Gregory Eric Howard

Philipp Steinmann

Christoph Dirnecker

Alfred Haeusler

Badih El-Kareh

Michael Schober

Manfred Schiekofer

Thomas Scharnagl

Phillipp Steinmann

Carl David Willis

Alfred Hausler

An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors (), each having a buried collector region ('). A carbon-bearing diffusion barrier () is disposed over the buried collector region (&#x2032;), to inhibit the diffusion of dopant from the buried collector region (&#x2032;) into the overlying epitaxial layer (). The diffusion barrier () may be formed by incorporating a carbon source into the epitaxial formation of the overlying layer (), or by ion implantation. In the case of ion implantation of carbon or SiGeC, masks () may be used to define the locations of the buried collector regions (&#x2032;) that are to receive the carbon; for example, portions underlying eventual collector contacts () may be masked from the carbon implant so that dopant from the buried collector region (&#x2032;) can diffuse upward to meet the contact (). MOS transistors () including the diffusion barrier () are also disclosed.

Control of dopant diffusion from buried layers in bipolar integrated circuits

The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer () beneath the gate dielectric () and source and drain regions () of a MOS transistor. The carbon containing layer () will prevent the diffusion of dopants into the region () directly beneath the gate dielectric layer ().

Advanced CMOS using super steep retrograde wells

An integrated stacked capacitor comprises a first capacitor film () of polycrystalline silicide, a second capacitor film () and a first dielectric () sandwiched between the first capacitor film () and second capacitor film (). A second dielectric () and a third capacitor film () are provided. The second dielectric () is sandwiched between the second capacitor film () and third capacitor film (). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer () to form the first capacitor film (); applying a first dielectric (); applying a first metallization layer () to form the second capacitor film (); applying a second dielectric (); and applying a second metallization layer () to form the third capacitor film ().

Integrated stacked capacitor and method of fabricating same

An integrated circuit programmable structure () is formed for use a trim resistor and/or a programmable fuse. The programmable structure comprises placing heating elements () in close proximity to the programmable structure () to heat the programmable structure () during programming.

On chip heating for electrical trimming of polysilicon and polysilicon-silicon-germanium resistors and electrically programmable fuses for integrated circuits

An integrated stacked capacitor comprises a first capacitor film () of polycrystalline silicide (poly), a second capacitor film () and a first dielectric () sandwiched between the first capacitor film () and second capacitor film (). A second dielectric () and a third capacitor film () are provided. The second dielectric () is sandwiched between the second capacitor film () and third capacitor film (). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer () to form the first capacitor film (); applying a first dielectric (); applying a first metallization layer () to form the second capacitor film (); applying a second dielectric (); and applying a second metallization layer () to form the third capacitor film ().

A method of fabricating an epitaxial silicon-germanium layer for an integrated semiconductor device comprises the step of depositing an arsenic in-situ doped silicon-germanium layer, wherein arsenic and germanium are introduced subsequently into different regions of said silicon-germanium layer during deposition of said silicon-germanium layer. By separating arsenic from germanium any interaction between arsenic and germanium is avoided during deposition thereby allowing fabricating silicon-germanium layers with reproducible doping profiles.

Method of fabricating an epitaxial silicon-germanium layer and an integrated semiconductor device comprising an epitaxial arsenic in-situ doped silicon-germanium layer

Method of producing complementary SiGe bipolar transistors. In a method of producing complementary SiGe bipolar transistors, interface oxide layers () for NPN and PNP emitters (), are separately formed and emitter polysilicon () is separately patterned, allowing these layers to be optimized for the respective conductivity type.

Method of producing complementary SiGe bipolar transistors

A method for manufacturing a semiconductor device includes forming a buried layer of a semiconductor substrate. An active region is formed adjacent at least a portion of the buried layer. A first isolation structure is formed adjacent at least a portion of the buried layer. A second isolation structure is formed adjacent at least a portion of the active region. A base layer is formed adjacent at least a portion of the active region. A dielectric layer is formed adjacent at least a portion of the base layer, and then at least part of the dielectric layer is removed at an emitter contact location and at a sinker contact location. An emitter structure is formed at the emitter contact location. Forming the emitter structure includes etching the semiconductor device at the sinker contact location to form a sinker contact region. The sinker contact region has a first depth. The method may also include forming a gate structure. Forming the gate structure includes etching the sinker contact region thereby increasing the first depth of the sinker contact region to a second depth.

Structure of semiconductor device with sinker contact region

In a method of fabricating complementary bipolar transistors with SiGe base regions the base regions of the NPN and PNP transistors are formed one after the other over two collector regionsby epitaxial deposition of crystalline silicon-germanium layers. With this method the germanium profile of the SiGe layers can be freely selected for both NPN and PNP transistors in thus enabling complementary transistor performance to be optimized individually. The SiGe layerscan be doped with an n-type or p-type dopant during or after deposition of the silicon-germanium layers

Method of fabricating complementary bipolar transistors with SiGe base regions

The invention relates to a stacked capacitor () comprising a silicon base plate (), a poly-silicon center plate () arranged above the base plate (), a lower gate-oxide dielectric () arranged between the base plate () and the center plate (), a cover plate () made of a metallic conductor and arranged above the center plate (), and an upper dielectric () arranged between the center plate () and the cover plate (). The cover plate () and the base plate () are electrically connected to each other and together form a first capacitor electrode. The center plate () forms a second capacitor electrode. The invention further relates to an integrated circuit with such a stacked capacitor, as well as to a method for fabrication of a stacked capacitor as part of a CMOS process.

Stacked capacitor and method for fabricating same

In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.

Method of fabricating an integrated silicon-germanium heterobipolar transistor and an integrated silicon-germanium heterobipolar transistor

High-voltage bipolar transistors () in silicon-on-insulator (SOI) integrated circuits are disclosed. In one disclosed embodiment, an collector region () is formed in epitaxial silicon () disposed over a buried insulator layer (). A base region () and emitter () are disposed over the collector region (). Buried collector region () are disposed in the epitaxial silicon () away from the base region (). The transistor may be arranged in a rectangular fashion, as conventional, or alternatively by forming an annular buried collector region (). According to another disclosed embodiment, a high voltage transistor () includes a central isolation structure (), so that the base region () and emitter region () are ring-shaped to provide improved performance. A process for fabricating the high voltage transistor () simultaneously with a high performance transistor () is also disclosed.

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Munich, Germany

Scott G Balster