Agere Systems Guardian Corp.

Lucent Technologies Inc.

Agere Systems Inc.

Scott Francis Shive

Alvaro Maury

Seungmoo Choi

Stephen Carl Kuehne

Donald Thomas Cwynar

Felix Llevada

Timothy Edward Doyle

Yi Ma

Mahjoub Ali Abdelgadir

Melissa M Brown

A halo implant ( ) for an MOS transistor ( ) is formed in a semiconductor substrate ( ) at a shallow implant angle, relative to normal to the substrate surface ( ). A polysilicon gate structure ( ) is formed over a gate oxide ( ) and then a hard mask ( ), such as a TEOS-generated layer of silicon oxide, is deposited on an upper surface ( ) of the gate. The mask is etched with a blanket anisotropic etch to form a cap-shaped mask ( ). The shape of the cap causes the dopant for the halo implant to penetrate to a depth which follows the contour of the cap. Thus, halo implants may be formed which extend under the gate structure without the need for large angle implants and resultant shadowing problems caused by adjacent devices.

Method for fabricating MOS device with halo implanted region

The present invention provides a semiconductor device including large topography alignment marks, and a method of manufacture therefor. The method of manufacturing the semiconductor device includes forming an isolation trench and an alignment mark in a substrate to a substantially common depth, and forming an etch stop layer in the alignment mark.

Alignment mark having a protective oxide layer for use with shallow trench isolation

During formation of shallow-trench isolation (STI) structures during semiconductor processing, an additional oxide-reduction etching step is performed prior to chemical-mechanical processing. In one implementation wet-etching and/or sputter etch-back (SEB) is performed prior to applying a reverse-tone mask. In another implementation a wet etching step is performed after the reverse-tone mask is stripped. One significant result of each of these steps is a reduction in the height and width of at least some of the oxide horns that remain after the reverse-tone mask is stripped. As such, the oxide structures that need to be planarized during CMP will be smaller than those of the prior art. Moreover, since the resulting oxide structures that need to be planarized by CMP processing are smaller, the oxide layer can be initially applied at a smaller thickness than that of the prior art. As such, the duration of CMP processing can be correspondingly shorter, resulting in polished semiconductor wafer surfaces with greater uniformity than that provided by the prior art.

Additional etching to decrease polishing time for shallow-trench isolation in semiconductor processing

A method for making an integrated circuit preferably includes the steps of: forming a trench laterally adjacent an active region in a semiconductor substrate; forming a dielectric layer on the semiconductor substrate filling the trench and covering the active area; selectively etching the dielectric layer to remove at least a portion of the dielectric layer overlying the active region and to define a recess within the dielectric layer filling the trench to serve as an alignment mark; and polishing the selectively etched dielectric layer and leaving the alignment mark. The method may also include forming an optically opaque layer adjacent the polished dielectric layer and with the alignment mark causing a repeated alignment mark in the optically opaque layer. The alignment mark and/or repeated alignment mark may be used for alignment in a subsequent processing step. The alignment mark can be made with a step height which is greater than a conventional alignment mark formed by the step height difference between the active area and the dielectric layer of the trench. Accordingly, variations in polishing, for example, will not obscure or remove the alignment mark made in accordance with the present invention.

Method for making an integrated circuit including alignment marks

A trench isolation structure is fabricated using high pressure and low temperature. A substrate is provided within which a trench is formed. The trench walls are annealed in nitrogen at a pressure above atmospheric pressure to remove silicon damage caused by plasma etching. The exposed side walls of the trench are oxidized at a pressure above atmospheric pressure to form an oxidized layer. The trench is filled with an oxide. Optionally, re-oxidation densification may be performed at a pressure above atmospheric pressure and a temperature in the range of about 600&deg; C. to about 800&deg; C.

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Orlando, FL, United States of America

Scott Francis Shive