International Business Machines Corporation

Other

Infineon Technologies Ag

Siemens Aktiengesellschaft

Infineon Technologies North America Corp.

Scott David Halle

Allen H Gabor

Arpan Pravin Mahorowala

Katherina E Babich

Marie Angelopoulos

Dirk Pfeiffer

Sean David Burns

Ravi K Bonam

Jack Allan Mandelman

Matthew Earl Colburn

Helen Wang

Jeffrey P Gambino

Michael P Belyansky

Anuja Desilva

Effendi Leobandung

Alfred Grill

Herbert Lei Ho

Thomas W Dyer

Nelson M Felix

Richard Anthony Conti

Jochen C Beintner

Vishnubhai Vitthalbhai Patel

David M Dobuzinsky

Henning Haffner

Haoren Zhuang

Ioana C Graur

Todd Christopher Bailey

Mark A Jaso

Robin Hsin Kuo Chao

Mary Elizabeth Weybright

Erwin Hammerl

Gill Yong Lee

Radhika Srinivasan

Thomas S Rupp

Richard C Johnson

Zachary Baum

Marshal A Miller

Bruce Bennett Doris

Carl John Radens

David V Horak

Daniel C Edelstein

Oleg Gluschenkov

Ramachandra Divakaruni

Theodore Gerard Van Kessel

Timothy Joseph Dalton

Fee Li Lie

James William Adkisson

Richard Stephan Wise

Wu-Song S Huang

Laertis Economikos

Hemantha Kumar Wickramasinghe

Gary Bela Bronner

Dario Leonardo Goldfarb

Pushkara Rao Varanasi

Gauri V Karve

Paul Charles Jamison

Wesley Charles Natzle

David Edward Kotecki

K Paul Muller

Ulrike Gruening

Christopher P Ausschnitt

Rama Divakaruni

Howard Smith Landis

William J Cote

Heon Lee

Hongwen Yan

Scott Marshall Mansfield

Colin J Brodsky

Daniel A Corliss

Rajesh Rengarajan

Jeremy K Stephens

Philip C Hobbs

Rajeev Malik

Christopher Frederick Robinson

Derren Neylon Dunn

Dale Warner Martin

Axel Christoph Brintzinger

Andreas Knorr

Jeffrey John Welser

Donald J Samuels

Scott Josef Bukofsky

Gangadhara Raja Muthinti

Martin Burkhardt

Kyong Min Yeo

Len Yuan Tsou

Klaus Herold

Ranee Wai-Ling Kwong

Luciana Meli

Prakash Chimanlal Dev

Tadashi Mitsui

Jason E Meiring

Juergen Wittmann

Chumeng Zheng

ChorngLii Hwang

Norbert Arnod

The embodiments herein describe authenticating a photomask used to fabricate an IC or a wafer. Because the IC may have been fabricated at a third-party IC manufacturer, the customer may want to ensure the manufacturer did not mistakenly use an incorrect mask, or that the mask was not altered or replaced with a rogue mask by a nefarious actor. That is, the embodiments herein can be used to identify when an IC manufacture (whether trusted or not) mistakenly used the wrong photomask, or to verify that a third-party IC manufacturer did not tamper with or replace the authentic photomask with a rogue mask. Advantageously, the embodiments herein can create a secure IC fabrication process to catch mistakes as well as ensure that non-trusted third-parties did not introduce defects into the IC.

Secure fingerprinting of a trusted photomask

Predictive multi-stage modelling for complex semiconductor device manufacturing process control is provided. In one aspect, a method of predictive multi-stage modelling for controlling a complex semiconductor device manufacturing process includes: collecting geometrical data from metrology measurements made at select stages of the manufacturing process; and making an outcome probability prediction at each of the select stages using a multiplicative kernel Gaussian process, wherein the outcome probability prediction is a function of a current stage and all prior stages. Machine-learning models can be trained for each of the select stages of the manufacturing process using the multiplicative kernel Gaussian process. The machine-learning models can be used to provide probabilistic predictions for a final outcome in real-time for production wafers. The probabilistic predictions can then be used to select production wafers for rework, sort, scrap or disposition.

Predictive multi-stage modelling for complex process control

Techniques for secure and tamper-resistant wafer identification using a unique wafer fingerprint are provided. In one aspect, a method for wafer authentication includes: placing, at each level of fabrication of chips on the wafer, reference structures across the chips; inspecting the wafer at each level of the fabrication; and performing at least one of overlay and scatterometry measurements of the reference structures to use as a unique fingerprint for authenticating the wafer that has been inspected. A method for authentication throughout a process flow for fabrication of chips on a wafer is also provided, as is a wafer having chips and reference structures placed across the chips at each level of the chips to provide a unique fingerprint for authenticating the wafer.

Secure wafer inspection and identification

Systems, methods and computer program products generally include a vector by vector subtraction method per wafer. A first layer is exposed to form a pattern image on a wafer and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a baseline reference are measured. The first layer is then reworked and exposed to form the same pattern image and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a first layer are measured. The overlay data of the reworked first layer is subtracted from the overlay data of the first layer to provide an overlay difference at each of the multiple locations. The overlay difference is converted to a pre-correction factor of a magnitude opposite that of the overlay difference and is applied to exposure of a second layer provided on the first layer.

Baseline overlay control with residual noise reduction

A method comprises: defining a set of rules for an inspection and detection of a defect in two or more electronic devices on a semiconductor chip, the set of rules being based on a modulation transfer function providing a response as contrast versus spatial frequency of the pattern spacings of the two or more electronic devices on the semiconductor chip; generating two or more care areas for two or more pattern spacings of the electronic devices on the semiconductor chip using a hierarchical set of spacing rules; and inspecting the two or more pattern spacings of the electronic devices on the semiconductor chip for defects.

Care area generation by detection optimized methodology

A photomask lithography simulation model is created for making a semiconductor chip. Poor metrology is filtered and removed from a contour-specific metrology dataset to improve performance of the photomask. Filtering is performed by the application of a weighting scheme.

Process-metrology reproducibility bands for lithographic photomasks

A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.

Resist having tuned interface hardmask layer for EUV exposure

Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating an angled template mask that extends across and resides at an angle with respect to such spacer gratings. Angled, cut spacer gratings are etched into a second layer using the angled template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer.

Metrology marks for unidirectional grating superposition patterning processes

A method for forming a mask layout is described. A plurality of phase shapes are formed on either side of a critical feature of a design layout of an intergrated circuit chip having a plurality of critical features. A plurality of transition edges are identified from the edges of each phase shape. Each transition edge is parallel to critical feature. A transition space is identified as defined by one of the group including two transition edges and one transition edge. A transition polygon is formed by closing each transition space with at least one closing edge. Each transition polygon is transformed into a printing assist feature. A mask layout is formed from the printing assist features and critical features.

Mask layout formation

A lithographic structure comprising: an organic antireflective material disposed on a substrate, and a silicon antireflective material disposed on the organic antireflective material. The silicon antireflective material comprises a crosslinked polymer with a SiObackbone, a chromophore, and a transparent organic group that is substantially transparent to 193 nm or 157 nm radiation. In combination, the organic antireflective material and the silicon antireflective material provide an antireflective material suitable for deep ultraviolet lithography. The invention is also directed to a process of making the lithographic structure.

Process of making a lithographic structure using antireflective materials

A method of forming a semiconductor device having a substrate, an active region and an inactive region includes: forming a hardmask layer over the substrate; transferring a first pattern into the hardmask layer in the active region of the semiconductor device; forming one or more fills in the inactive region; forming a cut-away hole within, covering, or partially covering, the one or more fills to expose a portion of the hardmask layer, the exposed portion being within the one or more fills; and exposing the hardmask layer to an etchant to divide the first pattern into a second pattern including at least two separate elements.

Method of forming a semiconductor device having a cut-way hole to expose a portion of a hardmask layer

A lithographic structure comprising: an organic antireflective material disposed on a substrate; and a silicon antireflective material disposed on the organic antireflective material. The silicon antireflective material comprises a crosslinked polymer with a SiObackbone, a chromophore, and a transparent organic group that is substantially transparent to 193 nm or 157 nm radiation. In combination, the organic antireflective material and the silicon antireflective material provide an antireflective material suitable for deep ultraviolet lithography. The invention is also directed to a process of making the lithographic structure.

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Hopewell Junction, NY, United States of America

Scott David Halle