International Business Machines Corporation

Scott D Allen

Richard Stephan Wise

Huilong Zhu

Steven J Holmes

Clement Hsingjen Wann

Cyril Cabral, Jr

Zhijiong Luo

Christian Lavoie

Wai-Kin Li

Dirk Pfeiffer

Brian Joseph Greene

Rajarao Jammy

Chun-Yung Sung

Katherina E Babich

Sunfei Fang

Arpan Pravin Mahorowala

Colin J Brodsky

Kevin K Dezfulian

Hung Y Ng

Kangguo Cheng

Kuang-Jung Chen

Kevin R Winstel

Xi Li

Chris A Simoneau

Sadanand Vinayak Deshpande

Huihang Dong

Kenneth A Bandy

Bradley J Morgenfeld

Alexei A Gridnev

Geoffrey W Coates

Jay J Farmer

Anna E Cherian

A stack of a dielectric material layer and a metallic material layer are formed on a substrate. A first organic planarization layer, a non-metallic hard mask layer, and a photoresist layer are sequentially deposited over the metallic material layer. The photoresist layer is lithographically patterned, and the pattern in the photoresist layer is transferred through the non-metallic hard mask layer, the first organic planarization layer, and the metallic material layer to form a cavity. A second organic planarization layer is deposited within the cavity and over remaining portions of the photoresist layer. The second organic planarization layer and the photoresist layer are recessed, and the non-metallic hard mask layer is subsequently removed. Remaining portions of the first and second organic planarization layers are simultaneously removed to provide physically exposed surfaces of the patterned metallic material layer and a top surface of the dielectric material layer.

Metallic mask patterning process for minimizing collateral etch of an underlayer

An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

Opto-thermal annealing methods for forming metal gate and fully silicided gate-field effect transistors

Solutions for solutions for utilizing Inverse Reactive Ion Etching lag in double patterning contact formation are disclosed. In one embodiment, a method includes providing a CMOS device including: an NMOS device having an NMOS gate and a PMOS device having a PMOS gate; a shallow trench isolation located between the NMOS device and the PMOS device; and an inter-level dielectric located over the NMOS device, the PMOS device and the shallow trench isolation; performing a double-patterning etch process on the CMOS device under conditions causing inverse reactive ion etching lag, the performing including forming a first opening, a second opening and a third opening, the second opening being wider than the first opening, and the third opening being contiguous with the second opening; and forming a first contact in the first opening and forming a second contact in both of the second opening and the third opening.

Utilizing inverse reactive ion etching lag in double patterning contact formation

Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.

Opening hard mask and SOI substrate in single process chamber

Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided.

Techniques for patterning features in semiconductor devices

A method for reducing the size of a patterned semiconductor feature includes forming a first layer over a substrate to be patterned, and forming a photoresist layer over the first layer. The photoresist layer is patterned so as to expose portions of the first layer, and the exposed portions of the first layer are removed in a manner so as to create an undercut region beneath the patterned photoresist layer. The patterned photoresist layer is reflowed so as to cause reflowed portions of the patterned photoresist layer to occupy at least a portion of the undercut region.

Method for post lithographic critical dimension shrinking using thermal reflow process

Opto-thermal annealing methods for forming metal gate and fully silicided gate field effect transistors

The embodiments of the invention generally relate to an etching process, and more particularly to an etch processing for improving the yield of dielectric contacts on nickel silicides. An oxygen-free feedgas is used in an etching process to reduce or eliminate residuals, including oxidation and consumption of the silicide layer, at the contact surface. The contact resistance at contact surface is reduced, thereby improving the performance of the device.

Etch process for improving yield of dielectric contacts on nickel silicides

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Ledgewood, NJ, United States of America

Scott D Allen