Rca Inc.

Scott C Blackstone

Lubomir L Jastrzebski

John F Corboy, Jr

Robert H Pagliaro, Jr

A vertical IGFET comprising a substantially planar silicon wafer with a source electrode on one major surface and a drain electrode on the opposite major surface is disclosed. An insulated gate electrode, which includes a conductive finger portion surrounded by an insulating layer, is internally disposed in the silicon wafer such that a predetermined voltage applied to the gate electrode will regulate a current flow between the source and drain electrodes. The device is fabricated utilizing an epitaxial lateral overgrowth technique for depositing monocrystalline silicon over the insulated gate which is disposed on a silicon substrate.

Vertical IGFET with internal gate and method for making same

A monocrystalline silicon layer is formed on a mask layer on a semiconductor substrate. An apertured mask layer is disposed on the substrate, and an epitaxial layer is then grown by a two-step deposition/etching cycle. By repeating the deposition/etching cycle a predetermined number of times, monocrystalline silicon will be grown from the substrate surface, through the mask aperture, and over the mask layer.

Method for growing monocrystalline silicon through mask layer

Method for growing monocrystalline silicon on a mask layer

A method for forming closely spaced conductors suitable for use, for example, in CCD's and MESFET's is described utilizing an edge diffusion technique to convert exposed edge portions of a polycrystalline silicon layer to a non-etchable form. The converted portions are precisely and accurately formed to serve as spacers, thereby defining a narrow gap between adjacent conductive lines.

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Hopewell, NJ, United States of America

Scott C Blackstone