Sunrise Memory Corporation

Crossbar, Inc.

Sandisk 3d LLC

Glo Ab

Black Peak LLC

Applied Materials, Inc.

Other

Sandisk Technologies Inc.

Matrix Semiconductor, Inc.

Svensson, Carl Patrik Theodor

Lemay, Cynthia

Romano, Linda

Herner, Scott Brad

Thompson, Daniel Bryce

Scott Brad Herner

Eli Harari

Wu-Yi Henry Chien

Jie Zhou

Christopher John Petti

Hagop A Nazarian

Daniel Bryce Thompson

Robert D Norman

Sung Hyun Jo

Linda T Romano

Tanmay Kumar

Tianhong Yan

Khandker N Quader

Siu Lung Chan

Sayeef Salahuddin

Frank Sai-Keung Lee

Mehrdad Mofidi

Cynthia Lemay

Harry Yue Gee

Sandeep A Desai

Roy E Scheuerlein

Martin F Schubert

James Montague Cleeves

Maitreyee Mahajani

Steve G Ghanayem

Michael A Vyvoda

Abhijit Bandyopadhyay

Carl Patrik Theodor Svensson

Andrew J Walker

George Samachisa

Mark Harold Clark

Steven J Radigan

Steven Patrick Maxwell

Natividad Vasquez

Johan Knall

Manuel Hernandez

Sung-Hyun Jo

Xiaoming Ji

Manuel Anselmo Hernandez

A thin-film storage transistor includes a charge storage film provided between a channel region and a gate conductor where the charge storage film includes a tunneling dielectric layer formed adjacent the channel region and a charge trapping layer formed adjacent the tunneling dielectric layer. In some embodiments, the charge trapping layer is a layer including silicon, silicon oxide and silicon nitride materials. In one embodiment, the charge trapping layer is a layer including a mixture of silicon, silicon oxide and silicon nitride materials, where the silicon oxide and silicon nitride may or may not be their respective stoichiometric compounds.

Thin film storage transistor with silicon oxide nitride charge trapping layer

An electronic device with embedded access to a high-bandwidth, high-capacity fast-access memory includes (a) a memory circuit fabricated on a first semiconductor die, wherein the memory circuit includes numerous modular memory units, each modular memory unit having (i) a three-dimensional array of storage transistors, and (ii) a group of conductors exposed to a surface of the first semiconductor die, the group of conductors being configured for communicating control, address and data signals associated the memory unit; and (b) a logic circuit fabricated on a second semiconductor die, wherein the logic circuit also includes conductors each exposed at a surface of the second semiconductor die, wherein the first and second semiconductor dies are wafer-bonded, such that the conductors exposed at the surface of the first semiconductor die are each electrically connected to a corresponding one of the conductors exposed to the surface of the second semiconductor die. The three-dimensional array of storage transistors may be formed by NOR memory strings.

Device with embedded high-bandwidth, high-capacity memory using wafer bonding

A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

Vertical thin-film transistor and application as bit-line connector for 3-dimensional memory arrays

Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.

Methods for forming multilayer horizontal NOR-type thin-film memory strings

A thin-film storage transistor in a NOR memory string has a gate dielectric layer that includes a silicon oxide nitride (SiON) tunnel dielectric layer. In one embodiment, the SiON tunnel dielectric layer has a thickness between 0.5 to 5.0 nm thick and an index of refraction between 1.5 and 1.9. The SiON tunnel dielectric layer may be deposited at between 720° C. and 900° C. and between 100 and 800 mTorr vapor pressure, using an LPCVD technique under DCS, NO, and NHgas flows. The SiON tunnel dielectric layer may have a nitrogen content of 1-30 atomic percent (at %).

Silicon oxide nitride tunnel dielectric for a storage transistor in a 3-dimensional NOR memory string array

A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines ('word line stacks') is reduced, which improves the structural stability of the word line stacks.

Methods for forming multi-layer vertical NOR-type memory string arrays

A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

3-dimensional NOR memory array with very fine pitch: device and method

A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

Staggered word line architecture for reduced disturb in 3-dimensional nor memory arrays

A thin-film storage transistor formed in a memory array above a planar surface of a semiconductor substrate, includes (a) first and second planar dielectric layers, each being substantially parallel the planar surface of the semiconductor substrate; (b) a first semiconductor layer of a first conductivity having an opening therein; (c) second and third semiconductor layers of a second conductivity type opposite the first conductivity type, located on two opposite sides of the first semiconductor layer; (d) a charge-storage layer provided in the opening adjacent and in contact with the first semiconductor layer; and (e) a first conductor provided in the opening separated from the first semiconductor layer by the charge storage layer, wherein the first, second and third semiconductor layers are each provided as a planar layer of materials between the first and second dielectric layers. In this configuration, the first, second and third semiconductor layers and the first conductor provide a channel region, a drain region, a source region and a gate electrode of the thin-film storage transistor.

Thin-film storage transistors in a 3-dimensional array of nor memory strings and process for fabricating the same

Memory device including modular memory units and modular circuit units for concurrent memory operations

Process for forming a vertical thin-film transistor that serves as a connector to a bit-line of a 3-dimensional memory array

Methods for forming multi-layer vertical nor-type memory string arrays

A process for forming an antimony-doped silicon-containing layer includes: (a) depositing by chemical vapor deposition the antimony-doped silicon-containing layer above a semiconductor structure, using an antimony source gas and a silicon source gas or a combination of the silicon source gas and a germanium source gas; and (b) annealing the antimony-doped silicon-containing layer at a temperature of no greater than 800&#xb0; C. The antimony source gas may include one or more of: trimethylantimony (TMSb) and triethylantimony (TESb). The silicon source gas comprises one or more of: silane, disilane, trichlorosilane, (TCS), dichlorosilane (DCS), monochlorosilane (MCS), methylsilane, and silicon tetrachloride. The germanium source gas comprises germane.

Method for in situ preparation of antimony-doped silicon and silicon germanium films

A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stacks to create corresponding cavities in the active layers; (f) filling the cavities in the active stacks by a metallic or conductor material; (g) recessing the dielectric layer from the exposed sidewalls of the active stacks; and (h) filling recesses in the dielectric layer by a third semiconductor layer of a second conductivity opposite the first conductivity.

Fabrication method for a 3-dimensional NOR memory array

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San Jose, CA, United States of America

Scott Brad Herner