Lam Research Corporation

Saurabh J Ullal

Harmeet Singh

Anthony De La Llera

Rajinder Dhindsa

Keith Laurence Comendant

Vahid Vahedi

Yen-Kun Victor Wang

Jason Augustino

Allan Kent Ronne

Jaehyun Kim

William M Denty, Jr

Anthony J Norell

Hong Shih

John Edward Daugherty

Jon McChesney

Anthony J Ricci

Dean Jay Larson

Alan Jeffrey Miller

Tuochuan Huang

Daniel Arthur Brown

Frank Lin

Yan Fang

Chris Lee

Helene Del Puppo

Shibu Gangadharan

Thomas A Kamp

Thomas R Stevenson

John C Valcore, Jr

Konstantin Makhratchev

Matthew James Busche

Travis R Taylor

Michael S Kang

David Z Carman

Ed Santos

Larry Martinez

Daniel Byun

Anthony De Le Llera

Parasitic plasma in voids in a component of a plasma processing chamber can be eliminated by covering electrically conductive surfaces in an interior of the voids with a sleeve. The voids can be gas holes, lift pin holes, helium passages, conduits and/or plenums in chamber components such as an upper electrode and a substrate support.

Parasitic plasma prevention in plasma processing chambers

A showerhead electrode assembly for a plasma processing apparatus is provided. The showerhead electrode assembly includes a first member attached to a second member. The first and second members have first and second gas passages in fluid communication. When a process gas is flowed through the gas passages, a total pressure drop is generated across the first and second gas passages. A fraction of the total pressure drop across the second gas passages is greater than a fraction of the total pressure drop across the first gas passages.

Showerhead electrode assembly with gas flow modification for extended electrode life

The present invention provides a reliable, non-invasive, electrical test method for predicting satisfactory performance of electrostatic chucks (ESCs). In accordance with an aspect of the present invention, a parameter, e.g., impedance, of an ESC is measured over a frequency band to generate a parameter functions. This parameter function may be used to establish predetermined acceptable limits of the parameter within the frequency band.

System and method for testing an electrostatic chuck

A plasma confinement ring assembly with a single movable lower ring can be used for controlling wafer area pressure in a capacitively coupled plasma reaction chamber wherein a wafer is supported on a lower electrode assembly and process gas is introduced into the chamber by an upper showerhead electrode assembly. The assembly includes an upper ring, the lower ring, hangers, hanger caps, spacer sleeves and washers. The lower ring is supported by the hangers and is movable towards the upper ring when the washers come into contact with the lower electrode assembly during adjustment of the gap between the upper and lower electrodes. The hanger caps engage upper ends of the hangers and fit in upper portions of hanger bores in the upper ring. The spacer sleeves surround lower sections of the hangers and fit within lower portions of the hanger bores. The washers fit between enlarged heads of the hangers and a lower surface of the lower ring. The spacer sleeves are dimensioned to avoid rubbing against the inner surfaces of the hanger bores during lifting of the lower ring.

Plasma confinement ring assembly for plasma processing chambers

A method for optimizing a dechuck sequence, which includes removing a substrate from a lower electrode. The method includes performing an initial analysis to determine if a first set of electrical characteristic data of a plasma formed during the dechuck sequence traverses a threshold values. If so, turning off the inert gas. The method also includes raising the lifter pins slightly from the lower electrode to move the substrate in an upward direction. The method further includes performing a mechanical and electrical analysis, which includes comparing a first set of mechanical data, which includes an amount of force exerted by the lifter pins, against a threshold value. The mechanical and electrical analysis also includes comparing a second set of electrical characteristic data against a threshold value. If both traverse the respective threshold value, removes the substrate from the lower electrode since a substrate-released event has occurred.

Methods and arrangement for plasma dechuck optimization based on coupling of plasma signaling to substrate position and potential

Components of a plasma processing apparatus includes a backing member with gas passages attached to an upper electrode with gas passages. To compensate for the differences in coefficient of thermal expansion between the metallic backing member and upper electrode, the gas passages are positioned and sized such that they are misaligned at ambient temperature and substantially concentric at an elevated processing temperature. Non-uniform shear stresses can be generated in the elastomeric bonding material, due to the thermal expansion. Shear stresses can either be accommodated by applying an elastomeric bonding material of varying thickness or using a backing member comprising of multiple pieces.

Upper electrode backing member with particle reducing features

A recirculation system of a substrate support on which a semiconductor substrate is subjected to a multistep process in a vacuum chamber, the system comprising a substrate support having at least one liquid flow passage in a base plate thereof, an inlet and an outlet in fluid communication with the flow passage, a supply line in fluid communication with the inlet, and a return line in fluid communication with the outlet; a first recirculator providing liquid at temperature Tin fluid communication with the supply line and the return line; a second recirculator providing liquid at temperature Tin fluid communication with the supply line and the return line, temperature Tbeing at least 10&#xb0; C. above temperature T; a pre-cooling unit providing liquid at temperature Tconnected to the inlet and the outlet, temperature Tbeing at least 10&#xb0; C. below T; a pre-heating unit providing liquid at temperature Tconnected to the inlet and the outlet, temperature Tbeing at least 10&#xb0; C. above T; a controller operable to selectively operate valves of the recirculation system to recirculate liquid between the flow passage and the first recirculator, the second recirculator, the pre-cooling unit or the pre-heating unit.

Apparatus and method for temperature control of a semiconductor substrate support

Showerhead electrode assemblies are disclosed, which include a showerhead electrode adapted to be mounted in an interior of a vacuum chamber; an optional backing plate attached to the showerhead electrode; a thermal control plate attached to the backing plate or to the showerhead electrode at multiple contact points across the backing plate; and at least one thermally and electrically conductive gasket separating the backing plate and the thermal control plate, or the backing plate and showerhead electrode, at the contact points. Methods of processing semiconductor substrates using the showerhead electrode assemblies are also disclosed.

Showerhead electrode assemblies for plasma processing apparatuses

A plasma processing chamber, which includes an upper electrode assembly, a lower electrode assembly, and a plasma confinement assembly. The upper electrode assembly includes an upper electrode, a backing member, the backing member attachable to an upper surface of the upper electrode, and a guard ring surrounding an outer surface of the backing member and located above the upper surface of the upper electrode, wherein the guard ring is configured to provide an inner gap between the outer surface of the backing member and an inner periphery of the guard ring. The lower electrode assembly is adapted to receive a semiconductor substrate. The plasma confinement assembly is separated from an outer periphery of the upper electrode and the backing member by the guard ring.

Plasma processing chamber with guard ring for upper electrode assembly

A method for providing substantially similar chamber condition before each wafer process operation in a semiconductor process chamber is provided. The method allows for prevention of transport of particle and metal contamination from chamber surfaces to the processed wafer. The method initiates with depositing a silicon containing layer over an inner surface of an empty semiconductor process chamber. Then, a wafer is introduced into the semiconductor process chamber after depositing the silicon containing layer. Next, a process operation is performed on the wafer. The process operation deposits a residue on the silicon containing layer. Next, an in-situ cleaning process is initiated upon completion of the processing operation and removal of the wafer. The process initiation includes flowing a fluorine containing gas into the semiconductor process chamber, and establishing a pressure within the semiconductor process chamber capable of allowing a plasma created from the fluorine containing gas to clear the silicon containing layer covering the inner surface of the processing chamber. A semiconductor processing chamber having a silicon containing pre-coat is also provided.

In-situ pre-coating of plasma etch chamber for improved productivity and chamber condition control

A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.

Method to improve profile control and N/P loading in dual doped gate applications

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South San Francisco, CA, United States of America

Saurabh J Ullal