Nxp USA, Inc.

Nxp B.v.

Saumitra Raj Mehrotra

Bernhard Grote

Ljubo Radic

Xin Lin

Ronghua Zhu

Vishnu Khemka

Mark Edward Gibson

Xu Cheng

Tanuj Saxena

Kejun Xia

Tania Tricia-Marie Thomas

Provided is a semiconductor device that includes: a semiconductor substrate having a first doped region of a first doping type and a second doped region of a second doping type, the first doped region being beneath but immediately adjacent to, the second doped region, with the first doping type being opposite the second doping type, thereby forming a junction region between the first doped region and the second doped region; and an additional layer that has been deposited above the junction region having similar mechanical properties as the semiconductor substrate. The additional layer covers at least 50% of a projection area of the junction region. The second doped region has a top surface, the additional layer has a bottom surface, and at least 90% of the bottom surface of the additional layer is electrically insulated from the top surface of the second doped region.

Semiconductor device with improved mechanical stress resistance

A transistor device includes a substrate, a first current-carrying region having a first lateral width, and a second current-carrying region. A first trench is formed between the first current-carrying region and the second current-carrying region. The first trench includes a first vertical component sidewall coupled to the first current-carrying region and a second vertical component sidewall coupled to the second current-carrying region. A first termination region includes a first termination portion coupled to the first current-carrying region, a second termination portion coupled to the second current-carrying region, and a first trench termination portion coupled to the first trench. The first trench and the first trench termination portion surround a portion of the first current-carrying region, and the second current-carrying region and the second termination portion surrounds a portion of the first trench and the first trench termination portion. A width of the first termination portion exceeds the first lateral width.

Transistor devices with termination regions

A transistor includes a trench formed in a semiconductor substrate. A conductive spacer is formed in the trench and offset from a first sidewall of the trench. A dielectric material is formed in the trench and surrounds the conductive spacer. A drift region is formed in the semiconductor substrate adjacent to the first sidewall and a first portion of a second sidewall of the trench. A drain region is formed in the drift region adjacent to a second portion of the second sidewall. A first gate region overlaps a portion of the drift region and is formed separate from the conductive spacer.

Laterally-diffused metal-oxide semiconductor transistor and method therefor

A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A gate region includes a conductive material filled in the trench. A drift region having a first conductivity type is formed in the semiconductor substrate adjacent to the second sidewall. A drain region is formed in the drift region and separated from the second sidewall by a first distance. A dielectric layer is formed at the top surface of the semiconductor substrate covering the gate region and the drift region between the second sidewall and the drain region. A field plate is formed over the dielectric layer and isolated from the conductive material and the drift region by way of the dielectric layer.

A method for manufacturing a Zener diode includes implanting an N-type Buried Layer (NBL) with an N-type dopant in a first epitaxial layer, wherein the NBL comprises an NBL opening excluding the N-type dopant. A P-type Buried Layer (PBL) having a peak PBL doping concentration below the NBL is implanted. A second epitaxial layer is grown over the NBL. A P-type region (Plink) is implanted to couple to the PBL above the NBL opening, and to couple the Plink to an Anode electrode. An N-type region (Nlink) is implanted to couple the NBL to a Cathode electrode.

Buried Zener design

Disclosed herein is a transistor structure that is formed by forming a sidewall spacer along a first vertical component sidewall of a trench wherein no sidewall spacer is formed along a second vertical component sidewall of the trench. During an etching of a dielectric layer in the trench, the sidewall spacer protects a first portion of the dielectric layer from being etched while a second portion of the dielectric layer along the second sidewall is etched. A portion of a control terminal can be formed in the space where the second portion is removed.

Transistor formed with spacer

A transistor device having a channel region including a portion located in a sidewall of semiconductor material of a trench and an extended drain region including a portion located in a lower portion of the semiconductor material of the trench. In one embodiment, a control terminal of the transistor device is formed by patterning a layer of control terminal material to form a sidewall in the trench and a field plate for the transistor device is formed by forming a conductive sidewall spacer structure along the sidewall of the control terminal material.

Transistor with extended drain region

A semiconductor device includes a trench in a semiconductor material having a device section and a termination section. A gate structure is located in the trench. With some embodiments, the transverse cross-sectional width of the termination section is wider than the transverse cross-sectional width of the device section.

Trench with different transverse cross-sectional widths

A method includes forming separate conductive trench structures in a trench and then removing an upper portion of one of the conductive structures where the remaining portion serves as field gate for a transistor. Removing the upper portion includes forming a second trench. The second trench is filled with a gate material that is used as a gate for the transistor. The transistor includes a source region for the transistor on the side of the trench and a drain region for the transistors on the other side of the trench, wherein the drain region includes a portion located at an upper portion of a semiconductor material. The transistor includes a channel region having a portion located along a sidewall of a trench.

Transistor trench with field plate structure

A method of forming a transistor device where an extended drain region is formed by performing angled ion implantation of conductivity dopants of a first conductivity type into the sidewalls and bottom portion of a trench. The bottom portion of the trench is then implanted with dopants of a second conductivity type. Source and drain regions are formed on opposing sides of the trench including in upper portions of the trench sidewalls. A channel region is formed in a trench sidewall below the source region. The trench includes a control terminal structure. After formation of the transistor device, the net conductivity type of the bottom portion of the trench is of the first conductivity type.

Transistor devices with extended drain regions located in trench sidewalls

Disclosed herein is a conductive structure that serves as both a control terminal and a field plate for a transistor. The transistor includes a channel region including a portion located in a vertical sidewall of semiconductor material that separates an upper level portion and a lower level portion of the semiconductor material. An extended drain region includes a portion located in the lower portion of the semiconductor material. The conductive structure is laterally adjacent to the vertical sidewall and includes a first vertical side and an opposite second vertical side with the first vertical side being closer to the vertical component sidewall. The first side is vertically closer to the lower level portion of the semiconductor material than the second vertical side.

Transistor with gate/field plate structure

A transistor device includes a channel region including a portion located in a vertical sidewall of semiconductor material and an extended drain region including a portion located in a lower portion of the semiconductor material. In one embodiment, a control terminal of the transistor device is formed by forming a conductive sidewall spacer structure adjacent to the sidewall and a field plate for the transistor device is formed by forming a second conductive sidewall spacer structure.

Vertical transistor with extended drain region

A semiconductor device includes a drain region for a transistor, a drain active area directly below the drain region, a drift area directly below an insolation structure, and an accumulation area directly below a gate structure of the transistor. The semiconductor device includes a first selectively doped implant region of a first concentration of a first conductivity type extending to a first depth. The first selectively doped implant region is located in the drift area, the drain active area, and the accumulation area. The semiconductor device includes a second selectively doped implant region of a second concentration of the first conductivity type and extending to a second depth less than the first depth. The second concentration is less than the first concentration. The second selectively doped implant region is located the drain active area, but not in the accumulation area. The second selectively doped implant region occupies a lateral portion of the drain active area that the first doped region does not occupy.

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Scottsdale, AZ, United States of America

Saumitra Raj Mehrotra