North American Philips Corporation

Philips Electronics North America Corporation

Koninklijke Philips Corporation N.V.

U.S. Philips Corporation

Satyendranath Mukherjee

Manjin J Kim

Barry M Singer

Gert W Bruning

Stephen L Wong

Emil Arnold

Dev Alok

Len-Yuan Tsou

Di-Son Kuo

Paul R Veldman

Mark Simpson

Naveed Majid

Armin F Wegener

Richard H Egloff

Johnny K Sin

Michael Amato

Manjin Kim

A method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor (MOSFET) is provided. Specifically, the present invention provides a method for applying an oxide layer to a silicon carbide substrate so that the oxide-substrate interface of the resulting SiC MOSFET is improved. The method includes forming the oxide layer in the presence of metallic impurities.

Method for improving inversion layer mobility in a silicon carbide metal-oxide semiconductor field-effect transistor

A lateral silicon carbide (SiC) semiconductor device includes a SIC substrate of a first conductivity type, a SiC epitaxial layer of the first conductivity type on the substrate and a SiC surface layer on the SiC epitaxial layer. The SiC surface layer has a SiC first region of the first conductivity type, a SiC lateral drift region of a second conductivity type opposite to that of the first conductivity type adjacent the first region and forming a p-n junction therewith, and a SiC second region of the second conductivity type spaced apart from the first region by the drift region. By providing the drift region with a variable doping level which increases in a direction from the first region to the second region, compact SiC semiconductor devices such as high-voltage diodes or MOSFETs can be formed which can operate at high voltages, high temperatures and high frequencies, thus providing a substantial advantage over known devices.

Lateral silicon carbide semiconductor device having a drift region with

An electrically erasable and programmable read only memory (EEPROM) includes an array of trench memory cells, with each memory cell having a semiconductor drain region adjacent a surface-adjoining portion of the trench. The EEPROM is provided with at least two overlapping metallization layers overlying the memory cells and separated from each other and from the trenches and the drain regions by regions of insulating material. The overlapping metallization layers contact the drain regions of the underlying memory cells through the insulating material. This configuration results in a memory array having a very high packing density.

Electrically erasable and programmable read only memory (EEPROM) having

An electrically erasable and programmable read only memory (EEPROM) is provided with an insulated control gate and an insulating floating gate in a trench in a semiconductor body. A dielectric layer is disposed along the sidewalls of the trench to separate the floating gate and the semiconductor body. The thickness of the dielectric layer along at least one sidewall of the trench is greater than the thickness of the dielectric layer along the other sidewalls of the trench in order to increase the programming speed due to a higher electric field in the gate oxide along the remaining sidewalls.

Electrically erasable and programmable read only memory with non-uniform

A method is set forth for forming a plurality of SOI transistors in a pattern beneath planarized reflective surfaces of a reflective display. This enables the formation of information pixels useful in devices, such as reflective LCD devices. A specific technique of providing the SOI transistors is set forth.

Method of manufacturing a reflective display

A high-voltage differential sensor includes an attenuator formed of two matched monolithic capacitance divider networks. Each divider network is formed of a series connection of monolithically integrated capacitors, which together generate an attenuated differential signal from a high-voltage differential input signal. The attenuated differential signal from the capacitance divider networks is then amplified and fed to a comparator, which generates a first output level when the high-voltage differential input signal is above a selected level, and generates a second output level when the high-voltage differential input signal is below the selected level. By using monolithically integrated capacitors in the divider networks of the attenuator, a simple, compact, low power, high performance high-voltage differential sensor is obtained.

High voltage differential sensor having a capacitive attenuator

A semiconductor device is provided having a substrate which includes a floating circuit well with turn on/turn off signals generated by a voltage drop proximate to at least one resistor contained therein, and having high-voltage interconnects to connect the drain terminals of a plurality of LDMOS transistors to the resistor in the floating well and wherein the transistors, resistor and floating well are combined into an integrated structure which eliminates the high voltage interconnect crossovers.

Semiconductor device configuration with multiple HV-LDMOS transistors

A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the first base region, the lateral edges of the second base region being substantially aligned with the lateral edges of the gate electrode; the first base region and the source region are formed by sequential implantation through the polysilicon gate electrode region using edges of the polysilicon gate electrode as a self-aligned mask, followed by implantation of the second base region without substantial lateral diffusion using the polysilicon gate electrode as a mask; and the polysilicon gate electrode is of a thickness sufficient to mask for selected depths of implantation in the first base region.

Vertical power MOS device with increased ruggedness and method of

A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the first base region, the lateral edges of the second base region being substantially aligned with the lateral edges of the gate electrode; the first base region and the source region are formed by sequential implantation through the polysilicon gate electrode region using the polysilicon gate electrode as a self-aligned mask, followed by implantation of the second base region without substantial lateral diffusion using the polysilicon gate electrode as a mask; and the polysilicon gate electrode is of a thickness sufficient to mask for selected depths of implantation in the first base region.

A power integrated circuit includes a substrate with an overlying epitaxial surface layer of opposite conductivity type. A semiconductor power device, such as a high-power diode or lateral MOS transistor, is located in the epitaxial layer and forms a p-n junction diode with the substrate. The power integrated circuit also includes a separate semiconductor well region in the epitaxial layer, in which one or more low-power semiconductor circuit elements are formed. In order to minimize the problem of latch up in the low-power circuit elements due to the injection of minority carriers from the substrate, the power integrated circuit is provided with a collector region and an isolation region between the power device and the well region having the low-power circuit elements.

Power integrated circuit with latch-up prevention

A nonvolatile trench memory device such as an EEPROM is made by a method which permits an extremely compact and simple configuration due to the use of precise and efficient self-alignment techniques. Oxide-capped polysilicon mesas, formed integrally with the control gates, form the word lines of the memory device, while drain metallization lines contact drain regions of the device and extend over the oxide-capped word lines to form the bit lines. The resulting device is extremely compact, since the self-aligned process permits tighter tolerances and the unique polysilicon mesa/oxide cap construction permits a more compact configuration.

Nonvolatile trench memory device and self-aligned method for making such

An Erasable and Programmable Read Only Memory (EEPROM) cell is provided with an insulated control gate and an insulating floating gate formed in a trench in a semiconductor body. A surface-adjoining drain region is provided alongside an upper portion of a sidewall of the trench, while a source region is provided alongside a lower portion of the trench sidewall, with a channel region extending along the sidewall of the trench between the source and drain regions. The EEPROM cell is programmed by hot electron injection through the sidewall of the trench alongside the channel region, and is erased by Fowler Nordhiem tunneling through a corner region in the bottom of the trench by creating a localized high electric field density in the corner region. In this manner, a highly compact, efficient and durable EEPROM cell is obtained.

Electrically erasable and programmable read only memory with trench

A lateral MOS transistor includes a semi-insulating field plate adjacent the surface of the device, over the drift region and extending laterally from the drain electrode toward the gate and source electrodes of the transistor. The field plate is connected at one end to the drain electrode, and at the other end to either the gate electrode of the source electrode. In order to improve the turn-on characteristics of the transistor, a surface-adjoining semiconductor top layer is provided in the drift region of the device, between the channel region and the drain region. This top layer is connected to the channel region at selected locations, and serves to improve device turn-on performance by causing a more rapid decrease in ON resistance at turn-on.

MOS transistor with semi-insulating field plate and surface-adjoining

A semiconductor switch comprising a lateral DMOS and a lateral IGT both of which can be fabricated in a monolithic integrated circuit. In operation the lateral DMOS stays on while the lateral IGT is switched off in order to reduce turn off power dissipation.

Growing community of inventors

Yorktown Heights, NY, United States of America

Satyendranath Mukherjee