Sun Microsystems, Inc.

Cisco Technology, Inc.

Satyanarayana Nishtala

William C Van Loo

Zahir Ebrahim

Kevin B Normoyle

Louis F Coffin, Iii

Leslie Dean Kohn

Luca Cafiero

Paul N Loewenstein

Charles E Narad

Mario Mazzola

Daniel E Lenoski

Philip R Manela

William Van Loo

Whay Sing Lee

Raghavendra J Rao

Sun-den Chen

Thomas L Lyon

Curtis R Priem

Howard Lee Davidson

Michael G Lavelle

Thomas P Webber

Kenneth Kitlas

Michael C Freda

Alan Lee Winick

Peter A Mehring

Guy Moffat

Anita Patel

Kenneth A Lown

Mohammed A Tantoush

Mark Ramon Imbertson

Jayarama N Shenoy

Alan W Lam

Dmitry Barsky

Tai-Yu Chou

Michael Yatziv

Louis F Coffin Iii

Sue K Lee

Raymond Ng

Winiie C Leung

Christopher R Owen

Philip Manela

Daniel Edward Lenoski

Thomas Lee Lyon

Techniques are provided for an access device, such as a Serial Attached Small Computer System Interface (SAS) expander, that is in communication with a storage device to subdivide the storage space of the storage device into a plurality of logical storage spaces, where the access device mediates storage and retrieval of data to and from the storage device. The access device maintains a unique identifier assigned to each of the logical storage spaces. Storage and retrieval of data to and from at least one of the logical storage spaces by way of the access device is based on the assigned unique identifier. The storage space may be subdivided using logical block addresses (LBAs) of the storage device without physically partitioning the available storage on the storage device.

Serial attached storage drive virtualization

This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.

System and methods for memory expansion

In one embodiment, a method includes determining if a power load requirement associated with a server arrangement is below a threshold. The server arrangement includes at least a first power supply and a second power supply, as well as a capacitor arrangement. The method also includes providing power to the server arrangement using the first power supply and not the second power supply when it is determined that the power load requirement is below the threshold, and providing the power to the server arrangement using the first power supply and the second power supply when it is determined that the power load requirement is not below the threshold.

Method and apparatus for providing power to a server platforms by using a capacitor to provide power during a second power supply transitioning on

A server power manager and method for dynamic server power management are generally described herein. The server power manager is configured to implement one or more server management policies that identify target server power consumption and/or target functionality for the server system. The server power manager determines an amount of excess processing capability and/or an amount of excess physical memory based on the target server power consumption and the target functionality. The server power manager may transition a processor core to a lower-operational state when at least a predetermined amount of excess processing capability is determined while maintaining server system functionality. The server power manager may transition a memory module to a lower-operational state when at least a predetermined amount of excess physical memory is determined while maintaining the server system functionality.

Server power manager and method for dynamically managing server power consumption

This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving first initialization data from a physical dual inline memory module (DIMM) and converting the first initialization data to second initialization data of a logical DIMM mapped to the physical DIMM. The example embodiment may further include programming a memory controller based on the second initialization data.

This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes detecting a memory command directed to a logical rand and a number of physical ranks mapped to the logical rank. The example embodiment may also include issuing the memory command to the number of physical ranks based on determining that the memory command is to be issued to the number of physical ranks.

An I/O module configured to operate in a memory module socket and method for extending a memory interface are generally described herein. The I/O module may include a serial-presence detection (SPD) device to indicate that the I/O module is an I/O device and to indicate one or more functions associated with the I/O module. The I/O module may also include a serial data controller to communicate serial data in accordance with a predetermined communication technique with a configurable switch of a host system over preselected system management (SM) bus address lines and unused system clock signal lines of the memory module socket. The predetermined communication technique may include a peripheral component interconnect express (PCIe), a Serial Advanced Technology Attachment (SATA), a Serial Attached Small Computer System Interface (SAS), a universal-serial bus (USB) or a switched-fabric (InfiniBand) communication technique.

Input-output module for operation in memory module socket and method for extending a memory interface for input-output operations

Embodiments of an I/O module, processing platform, and method for extending a memory interface are generally described herein. In some embodiments, the I/O module may be configured to operate in a memory module socket, such as a DIMM socket, to provide increased I/O functionality in a host system. Some system management bus address lines and some unused system clock signal lines may be reconfigured as serial data lines for serial data communications between the I/O module and a PCIe switch of the host system.

Input-output module, processing platform and method for extending a memory interface for input-output operations

In one embodiment, a direct memory access (DMA) disk controller used in hardware-assisted data transfer operations includes command receiving logic to receive a data transfer command issued by a processor. The data transfer command identifies one or more locations in memory and multiple distinct regions on one or more disks accessible to the DMA disk controller. The DMA disk controller further includes data manipulation logic to transfer data between the memory locations and the distinct regions on the disks according to the data transfer command.

Composite DMA disk controller for efficient hardware-assisted data transfer operations

Embodiments of the present invention provide methods and systems for data movement in data storage systems. For one embodiment, a physical data storage parcel containing a first type of data requiring a first type of processing and a second type of data requiring a second type of processing is created. The first type of data is transferred to a first memory address space via a direct memory access operation and the second type of data is transferred to a second memory address space via the direct memory access operation. For one embodiment, the first type of data and the second type of data are copied to physically distinct data storage mediums. In an alternative embodiment, the first type of data and the second type of data are copied to distinct data storage structures of the same device. Thus, the bulk memory access operations are performed via hardware, thereby reducing performance impact.

Method and system for data movement in data storage systems employing parcel-based data mapping

One embodiment of the present invention provides a system for detecting errors on a source-synchronous bus. The source-synchronous bus includes a plurality of data lines and a clock line. A transmitting mechanism configured to transmit data on the source-synchronous bus is coupled to the source-synchronous bus. A receiving mechanism configured to receive data from the source-synchronous bus is also coupled to the source-synchronous bus. An error detecting mechanism configured to detect errors on the source-synchronous bus is coupled to the receiving mechanism. The error detecting mechanism can detect errors on the plurality of data lines including errors that are caused by an error on the clock line.

Apparatus and method for error detection on source-synchronous buses

A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the network maintains a record of the sequence of packets that have passed through that node, and the state of each of the packets at the time it passed through, including a record of the last known good packet and its sequence number. When a producer node detects an error condition in an acknowledgment for a packet, resends all packets beginning with the last known good packet. Each consumer node is able to process or reject the resent packets, including packets that may already have been processed, which it is aware of due to the packet and state records for all packets. Strong ordering is thus supported, since the sending order of packets can be maintained for processing due to the resends, and nonidempotent commands are supported due to the consumer nodes' ability to determine whether they have already processed a given packet, and to send an acknowledge-done reply if that is the case.

System for dynamic ordering support in a ringlet serial interconnect

One embodiment of the present invention provides a system for defining signal timing for an integrated circuit device. The system operates by first creating a virtual timing reference plane for the integrated circuit device. A first signal line is then routed from a semiconductor die within the integrated circuit package to a first external connection of the integrated circuit package. Next, the system generates a first escape pattern for a first circuit trace on a printed circuit board from the first external connection to the virtual timing reference plane. This first escape pattern specifies a route from where the first external connection meets the printed circuit board to the virtual timing reference plane. Finally, the system establishes a first set of signal timings for a combination of the first signal line and the first circuit trace at the virtual timing reference plane.

Method and apparatus for defining signal timing for an integrated circuit device

A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width. In an alternative embodiment, the data transfer control system transfers the data words at substantially the full rate available, given the computer system's processor or clock speed and the width of the master bus, and the words are buffered before transference to the second bus. The speed of transference to the buffer is then not limited by the size of the second bus, but only by the size of the buffer, which preferably has an input bus at least as wide as that of the master bus. The system accommodates functional units of different sizes all to be couple to a master bus of a given size, where the different sizes may be larger or smaller than the master bus size, and accordingly the functional units can be built with optimal bus sizes for their particular functions without having to conform to a perhaps inappropriate, inefficient or expensive or wasteful master bus size.

System for multisized bus coupling in a packet-switched computer system

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Cupertino, CA, United States of America

Satyanarayana Nishtala