Motorola Corporation

Other

Satyamurthy Pullela

David Theodore Blaauw

Joseph W Norton

Abhijit Dharchoudhury

Tim J Edwards

Peter Redmond O'Brien

Stephen C Moore

Timothy J Edwards

Gopalakrishnan Vijayan

Rajendran Panda

Speed, size, and power trade-offs of a VLSI combinational circuit are optimized through iterative restructuring. First, timing analysis for the circuit is performed (102) to find the critical path through the circuit (104). Then, a gate is selected from the critical path (106), and a window is contracted around the gate (108). Within the window, alternate structures are constructed (110) and sized (112). The best alternative is substituted into the window (114), and the new circuit is resized (116). If the new circuit is not an improvement over the old (118), then the original window is replaced (120). In any case, this is repeated for each gate in the circuit (124). The entire process is then repeated until either user constraints are met, or the circuit doesn't change (122).

Optimizing combinational circuit layout through iterative restructuring

A slack time, based on a required and actual delay time, is calculated for each node in a circuit (302). For each element in the circuit, a sensitivity (304) and a figure of merit (306) is calculated. A variance is determined for the calculated figure of merits (308). The circuit element having the smallest absolute figure or merit is optimized when the variance is smaller than a predefined threshold (310, 312).

Method for optimizing element sizes in a semiconductor device

A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407, 409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit 'I-V' characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.

Complementary network reduction for load modeling

Simulation corrected sensitivity

A process and implementing computer system (13) for optimally sizing elements of an integrated circuit includes determining actual arrival times and required arrival times (403) for processed signals at all nodes within the integrated circuit and determining the slack or difference (405) between arrival and required times for each node. If the actual arrival time for a particular node is after the time required to meet a predetermined design constraint of the node (407), a determination (411) is made regarding the effect of that element on the nodal slack for an incremental increase in the size of that element. Thereafter an element is selected (413) for sizing increase (415) in accordance with a weighting function and the process is repeated until all of the nodes in the integrated circuit have positive slack times (407,409). One method of accomplishing a timing analysis step (303) includes an analytical circuit simulation technique (1000-1015) in which circuit 'I-V' characteristics are more precisely represented with a power series (1006) including a plurality of regional segmental approximations (901-907). Another method of timing analysis includes an equivalency methodology (1501-1513) of translating passive transistors to equivalent RC networks (801). In the overall optimization process, a method is provided (1701-1715) for automatically correcting transistor predicted sensitivities based upon a correction factor (1713). A multi-model timing method (1601-1619) is also illustrated (1601-1619) for synergistically combining fast and accurate circuit timing models to optimize the speed and accuracy of the design process itself while remaining within an accuracy threshold.

Accurate delay prediction based on multi-model analysis

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Satyamurthy Pullela