International Business Machines Corporation

Other

Freescale Semiconductor,inc.

Satya N Chakravarti

Dechao Guo

Keith Kwong Hon Wong

Huiming Bu

Ashima B Chakravarti

Thekkemadathil V Rajeevakumar

Subramanian Srikanteswara Iyer

Kwong Hon Wong

James Gardner Ryan

Byoung W Min

Chuck T Le

Judson Robert Holt

Fei Liu

Shreesh Narasimha

Wilbur David Pricer

Pranita Kulkarni

Victor Chan

Philip Joseph Oldiges

Stephen J Fonash

Lawrence G Heller

Irene Lennox McStay

Wilfried Ernst-August Haensch

Sundar Kumar Iyer

Paul L Garbarino

John Andrew Hiltebeitel

Donald A Miller

Timothy J Sullivan

Xiao-Chun Mu

After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

Replacement-gate-compatible programmable electrical antifuse

Techniques for incorporating nanotechnology into decoupling capacitor designs are provided. In one aspect, a decoupling capacitor is provided. The decoupling capacitor comprises a first electrode; an intermediate layer adjacent to the first electrode having a plurality of nanochannels therein; a conformal dielectric layer formed over the intermediate layer and lining the nanochannels; and a second electrode at least a portion of which is formed from an array of nanopillars that fill the nanochannels in the intermediate layer. Methods for fabricating the decoupling capacitor are also provided, as are semiconductor devices incorporating the decoupling capacitor design.

Nanopillar decoupling capacitor

Techniques for incorporating nanotechnology into electronic fuse (e-fuse) designs are provided. In one aspect, an e-fuse structure is provided. The e-fuse structure includes a first electrode; a dielectric layer on the first electrode having a plurality of nanochannels therein; an array of metal silicide nanopillars that fill the nanochannels in the dielectric layer, each nanopillar in the array serving as an e-fuse element; and a second electrode in contact with the array of metal silicide nanopillars opposite the first electrode. Methods for fabricating the e-fuse structure are also provided as are semiconductor devices incorporating the e-fuse structure.

Nanopillar E-fuse structure and process

A passive device structure includes an unpatterned metal gate layer formed in a passive device region of a semiconductor device; an insulator layer formed upon the unpatterned metal gate layer; a semiconductor layer formed upon the insulator layer; and one or more metal contact regions formed in the semiconductor layer; wherein the insulator layer prevents the metal gate layer as serving as a leakage current path for current flowing through a passive device defined by the semiconductor layer and the one or more metal contact regions.

Integration of passive device structures with metal gate layers

Method of forming a semiconductor device which includes the steps of obtaining a semiconductor substrate having a logic region and an STI region; sequentially depositing layers of high K material, metal gate, first silicon and hardmask; removing the hardmask and first silicon layers from the logic region; applying a second layer of silicon on the semiconductor substrate such that the logic region has layers of high K material, metal gate and second silicon and the STI region has layers of high K material, metal gate, first silicon, hardmask and second silicon. There may also be a second hardmask layer between the metal gate layer and the first silicon layer in the STI region. There may also be a hardmask layer between the metal gate layer and the first silicon layer in the STI region but no hardmask layer between the first and second layers of silicon in the STI region.

Method and structure for improving uniformity of passive devices in metal gate technology

A one-time programmable field effect transistor (FET) e-fuse has a silicided gate connected to the drain while the source is grounded. A voltage stimulus applied to the drain forces current to flow through the channel coupling the drain to the source. The magnitude of the current exceeding the threshold current density initiates electromigration of the source/drain silicide into the channel region, such that the source/drain of the FET is shorted to the substrate after programming. Under these constraints, the fuse device conducts current even when the transistor is in the off-state. The MOSFET e-fuse preferably uses a minimum channel length NFET/PFET and scales down its dimensions to conform to those allowed by the technology.

MOSFET fuse programmed by electromigration

Stress level of a nitride film is adjusted as a function of two or more of the following: identity of a starting material precursor used to make the nitride film; identity of a nitrogen-containing precursor with which is treated the starting material precursor; ratio of the starting material precursor to the nitrogen-containing precursor; a set of CVD conditions under which the film is grown; and/or a thickness to which the film is grown. A rapid thermal chemical vapor deposition (RTCVD) film produced by reacting a compound containing silicon, nitrogen and carbon (such as bis-tertiary butyl amino silane (BTBAS)) with NHcan provide advantageous properties, such as high stress and excellent performance in an etch-stop application. An ammonia-treated BTBAS film is particularly excellent in providing a high-stress property, and further having maintainability of that high-stress property over repeated annealing.

Material for contact etch layer to enhance device performance

A compact resistor is formed in an integrated circuit using many of the same steps as are employed in forming a trench capacitor for a DRAM cell; in particular depositing a layer of heavily doped germanium in the trench interior after the step of doping the substrate to form the bottom plate for the capacitor, depositing polysilicon having the required resistivity in the trench then removing the germanium and leaving only enough to form an ohmic contact in the trench bottom.

Simultaneous formation of deep trench capacitor and resistor

A method for removing surface oxide from polysilicon includes depositing a very thin layer of germanium (e.g. monolayers in thickness) over the polysilicon immediately before a subsequent polysilicon deposition step, and then heating the germanium-coated polysilicon in a vacuum to sublime (remove) volatile germanium oxide. This method is applied to formation of a trench capacitor, which uses either doped amorphous silicon or doped amorphous SiGe material in the formation of the electrodes.

Method for reducing surface oxide in polysilicon processing

A test structure and method for determining DRAM cell leakage. The cell leakage test structure includes a pair of buried strap test structures. Each buried strap test structure includes multiple trench capacitors formed in a silicon body. Each trench capacitor is connected to a trench sidewall diffusion by at least one buried strap. An n-well ring surrounds each buried strap test structure and divides the buried strap test structure into two separate array p-wells, one being a contact area and the other a leakage test area. The contact area includes contacts to the trench capacitor plates for the corresponding buried strap test structure. In one buried strap test structure, a layer of polysilicon, essentially covers the trench capacitors in the leakage test area to block source/drain region formation there. The other of the two buried strap test structures includes polysilicon lines simulating wordlines with source and drain regions form on either side. A buried n-band contacts the n-well rings, essentially forming an isolation tub around each array well. Cell leakage is measured by measuring leakage current in each buried strap test structure, individually, and then extracting individual leakage components from the measured result.

DRAM cell buried strap leakage measurement structure and method

A method for forming an integrated circuit device, and the product thereby produced, are disclosed. The disclosed method includes the steps of obtaining a substrate with a patterned gate conductor and cap insulator, forming a dielectric masking layer having at least one opening, and, using the opening in the dielectric masking layer as a mask, forming a trench capacitor which is self-aligned to the cap insulator edge. The method is particularly useful for a producing a DRAM device having a dense array region with self-aligned deep trench storage capacitors connected by buried straps.

Process for forming a high density semiconductor device

A method for forming an integrated circuit device, and the product thereby produced, are disclosed. The disclosed method includes the steps of obtaining a substrate with a patterned gate conductor and cap insulator, forming a dielectric masking layer having at least one opening, and, using the opening in the dielectric masking layer as a mask, forming a trench capacitor which is self-aligned to the cap insulator edge. The method is particularly useful for producing a DRAM device having a dense array region with self-aligned deep trench storage capacitors connected by buried straps.

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Hopewell Junction, NY, United States of America

Satya N Chakravarti