Spansion Llc.

Advanced Micro Devices Corporation

Fasl LLC

Satoshi Torii

Hidehiko Shiraiwa

Jaeyong Park

Youseok Suh

Lei Xue

Mark T Ramsbey

Mark W Randolph

Masaru Yano

Hideki Arakawa

Harpreet Kaur Sachar

Scott Allan Bell

Shenqing Fang

Chi K Chang

Kuo-Tung Chang

Darlene G Hamilton

Wei Zheng

Yi He

Chih-Yuh Yang

Zhizheng Liu

Joong Jeon

Amol Ramesh Joshi

Allison Holbrook

David H Matsumoto

Fatima Bathul

Michael Brennan

Alykhan Madhani

Lovejeet Singh

The present invention provides an apparatus and method for a non-volatile memory comprising at least one array of memory cells with shallow trench isolation (STI) regions between bit lines for increased process margins. Specifically, in one embodiment, each of the memory cells in the array of memory cells includes a source, a control gate, and a drain, and is capable of storing at least one bit. The array of memory cells further includes word lines that are coupled to control gates of memory cells. The word lines are arranged in rows in the array. In addition, the array comprises bit lines coupled to source and drains of memory cells. The bit lines are arranged in columns in the array. Also, the array comprises at least one row of bit line contacts for providing electrical conductivity to the bit lines. Further, the array comprises shallow trench isolation (STI) regions separating each of the bit lines along the row of bit line contacts.

Apparatus and method for a memory array with shallow trench isolation regions between bit lines for increased process margins

A memory system is provided including forming a memory gate stack having a charge trap layer over a semiconductor substrate, forming a protection layer to cover the memory gate stack, and forming a protection enclosure for the charge trap layer with the protection layer and the memory gate stack.

Memory system with protection layer to cover the memory gate stack and methods for forming same

A memory device () may include a substrate (), a dielectric layer () formed on the substrate () and a charge storage element () formed on the dielectric layer (). The memory device () may also include an inter-gate dielectric () formed on the charge storage element (), a barrier layer () formed on the inter-gate dielectric () and a control gate () formed on the barrier layer (). The barrier layer () prevents reaction between the control gate () and the inter-gate dielectric ().

Memory device with barrier layer

Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased cell in the present invention is a cell in the 'off' state. According to the present invention a cell is programmed by lowering the threshold voltage of the cell, thereby turning the cell 'on.' An array of cells is programmed read in a sector-by-sector method, wherein a sector consists of units situated diagonally adjacent to each other, and a unit consists of multiple parallel column-oriented pages.

Method and architecture for fast flash memory programming

A multiple dual bit integrated circuit system is provided that includes forming first address lines in a semiconductor substrate and forming a charge-trapping layer over the semiconductor substrate. A semiconductor layer is formed over the charge-trapping layer and second address lines are formed in the semiconductor layer to form a plurality of dual bit locations.

Multiple dual bit memory integrated circuit system

An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.

Integrated circuit memory system employing silicon rich layers

A device includes a substrate and multiple wells formed over the substrate and isolated from one another by dielectric trenches. The device further includes multiple memory elements formed over the wells, each of the memory elements extending approximately perpendicular to the wells and including a material doped with n-type impurities. The device also includes multiple source/drain regions, each source/drain region formed within one of multiple trenches and inside one of the plurality of wells between a pair of the memory elements, each of the source/drain regions implanted with p-type impurities. The device further includes a first substrate contact formed in a first one of the multiple trenches through a first one of the wells into the substrate and a second substrate contact formed in a second one of the multiple trenches through a second one of the wells into the substrate.

P-channel NAND in isolated N-well

A SONOS memory cell, formed within a semiconductor substrate, includes a bottom dielectric disposed on the semiconductor substrate, a charge trapping material disposed on the bottom dielectric, and a top dielectric disposed on the charge trapping material. Furthermore, the SONOS memory cell includes a word-line gate structure disposed on the top dielectric and at least one bit-line gate for inducing at least one inversion bit-line within the semiconductor substrate.

SONOS memory with inversion bit-lines

Methods for fabricating a flash memory device are provided. A method comprises forming a plurality of gate stacks overlying a substrate. Each gate stack comprises a charge trapping layer and a control gate. The control gate is a first distance from the substrate. Adjacent gate stacks are a second distance apart. A cell spacer material layer is deposited and is etched to form a spacer about sidewalls of each gate stack. A source/drain impurity doped region is formed adjacent a first gate stack and a last gate stack. The first distance and the second distance are such that, when a voltage is applied to a gate stack during a READ operation, a fringing field is created between the control gate of the gate stack and the substrate and is sufficient to invert a portion of the substrate between the gate stack and an adjacent gate stack.

Methods for fabricating flash memory devices

Systems and methods of fabricating a U-shaped memory device with a recessed channel and a segmented/separated ONO layer are provided. Multibit operation is facilitated by a separated ONO layer, which includes a charge trapping region on sidewalls of polysilicon gate structures adjacent to source/drain regions. Programming and erasing of the memory cells is facilitated by the relatively short distance between acting source regions and the gate. Additionally, short channel effects are mitigated by a relatively long U-shaped channel region that travels around the recessed polysilicon gate thereby adding a depth dimension to the channel length.

Recessed channel with separated ONO memory device

Novel fabrication methods permit concurrently forming wordlines, select gates and array source lines in NAND Flash. One method forms oxide and nitride layers of an ONO stack, implants dopants into a source line region to form and unite a source line structure to a source/drain region, forms another oxide and a high-dielectric over the nitride layer, removes the ONOA stack in the source line region, forms a gate oxide in the periphery, and forms an opening in the ONOA stack in an array source line region. The method deposits and selectively removes polysilicon and the high-dielectric concurrently forming wordline and select drain gate structures in bitline contact regions, and select source gate and source line structures in source line regions. The bitline and source line contact regions are implanted to form the source line structure in the source line region and unite the source/drain regions of select source gate structures.

Formation method of an array source line in NAND flash memory

For fabricating a memory device, spacers are formed to sides of word-line gates. In addition, aluminum oxide is formed as one of a liner layer or a cover layer to the spacers. The aluminum oxide has a chemical composition of AlOfor example. Such aluminum oxide may be used as an etch stop layer in a periphery region, a metal silicide block, and a hydrogen block for enhanced performance of the memory device.

Aluminum oxide as liner or cover layer to spacers in memory device

A method erases a memory cell of a semiconductor device that includes a group of memory cells. Each memory cell includes a group of storage regions. The method includes determining that each storage region of the group of storage regions of a first memory cell is to be erased and erasing the group of storage regions of the first memory cell via a single hot hole injection process.

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Sunnyvale, CA, United States of America

Satoshi Torii