Panasonic Intellectual Property Management Co., Ltd.

Panasonic Corporation

Matsushita Electric Industrial Co., Ltd.

Osaka University

Panasonic Holdings Corporation

Satoshi Nakazawa

Tetsuzo Ueda

Yusuke Kinoshita

Tsuyoshi Tanaka

Yoshiharu Anda

Naohiro Tsurumi

Ryosuke Maeda

Ryo Kajitani

Daisuke Ueda

Yasuhiro Uemoto

Tatsuo Morita

Masahiro Hikita

Yutaka Hirose

Takahiro Yamada

Hidetoshi Ishida

Hiroyuki Handa

Heiji Watanabe

Takayoshi Shimura

Takuji Hosoi

Masanori Nomura

Yuji Kudoh

Toshiyuki Takizawa

Kazushi Nakazawa

Yuta Nagatomi

Mikito Nozaki

Hong-An Shih

Satoru Ouchi

An on-state voltage measurement circuit includes a detecting switch element, a control unit, a resistive element, and a voltage detection unit. The control unit includes a signal output terminal and a reference potential terminal and controls the detecting switch element. The resistive element is connected between a source terminal of the detecting switch element and the reference potential terminal. A resistance value of the resistive element is greater than an on-state resistance of the detecting switch element. The control unit turns the detecting switch element on when the semiconductor switch element is turned on. The voltage detection unit detects, based on a voltage across the resistive element when the semiconductor switch element and the detecting switch element are both on, the on-state voltage of the semiconductor switch element connected between a drain terminal of the detecting switch element and the reference potential terminal.

On-state voltage measurement circuit

Current collapse of a normally-on type dual-gate bidirectional switch is suppressed. Dual-gate bidirectional switch includes first gate, first source, second gate, and second source. Control system includes first gate drive circuit, second gate drive circuit, and controller. Controller controls first gate drive circuit and second gate drive circuit. At the time of turning on dual-gate bidirectional switch and when the potential of first source is lower than the potential of second source, controller applies a first positive voltage for a first period between first gate and first source from first gate drive circuit, and applies a voltage smaller than the first positive voltage after the first period has elapsed.

Control system and control method for dual-gate bidirectional switch

In a switch system, a voltage clamping element is connected to a semiconductor switch in parallel. An active clamping circuit is connected between a control terminal and a first main terminal of the semiconductor switch. The active clamping circuit includes a first diode, a second diode, and a control switch. A second anode of the second diode is connected to a first anode of the first diode. The control switch is connected between the first anode of the first diode and the control terminal of the semiconductor switch. A second control unit controls the control switch. A breakdown voltage of the first diode is smaller than a clamp voltage of the voltage clamping element.

Switch system

A power loss of a switching device is suppressed. Circuit for a switching device is used in switching device. Switching device includes first path and second path. First path includes first field effect transistor and first inductor. Second path includes second field effect transistor and second inductor. First path and second path are connected in parallel to power supply. A first maximum current that is a maximum current during conduction of first field effect transistor is smaller than a second maximum current that is a maximum current during conduction of second field effect transistor. Circuit for a switching device includes processing part. Processing part executes a specific operation according to a voltage difference between voltage across first inductor and voltage across second inductor.

Circuit for switching device, switching system, and processing method for switching device

A switch system includes a bidirectional switch, a first gate driver circuit, a second gate driver circuit, a control unit, a first decision unit, and a second decision unit. The bidirectional switch includes a first source, a second source, a first gate, and a second gate. The first decision unit determines, based on a voltage at the first gate and a first threshold voltage, a state of the first gate in a first period in which a signal to turn OFF the first gate is output from the control unit to the first gate driver circuit. The second decision unit determines, based on a voltage at the second gate and a second threshold voltage, a state of the second gate in a second period in which a signal to turn OFF the second gate is output from the control unit to the second gate driver circuit.

A semiconductor device including: a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer. The gate insulator film includes a threshold value control layer that includes an oxynitride film.

Semiconductor device

Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an InAlGaN layer on the InAlN layer, where 0&#x3c;x&#x3c;1, 0&#x3c;y&#x3c;1, and x+y&#x3c;1; and a source electrode and a drain electrode formed on the InAlGaN layer.

Field effect transistor

An object is to achieve an increase in gain by reducing a current collapse, and reducing Cgd and Rg. A semiconductor device according to the present invention includes a substrate; a first semiconductor layer disposed on the substrate and made of a Group III nitride semiconductor; a second semiconductor layer disposed on the first semiconductor layer and made of a Group III nitride semiconductor; a gate electrode, a source electrode, and a drain electrode disposed on the second semiconductor layer; a first field plate electrode disposed on the second semiconductor layer; and a second field plate electrode disposed on the first field plate electrode, in which the first field plate electrode and the second field plate electrode are disposed between the gate electrode and the drain electrode.

A field effect transistor includes a nitride semiconductor multilayer structure formed on a substrate, a source electrode, a drain electrode, a gate electrode, an insulating film formed on the nitride semiconductor multilayer structure, and a field plate formed on and in contact with the insulating film, and having an end located between the gate electrode and the drain electrode. The insulating film includes a first film, and a second film having a dielectric breakdown voltage lower than that of the first film, and a thin film portion formed between the gate electrode and the drain electrode is formed in the insulating film. The field plate covers the thin film portion, and is connected to the source electrode in an opening.

A field effect transistor includes a nitride semiconductor layered structure that is formed on a substrate and includes a capping layer made of a compound represented by a general formula of InAlGaN (wherein 0&#x3c;x&#x2266;1, 0&#x2266;y&#x3c;1 and 0&#x3c;x+y&#x2266;1). A non-alloy source electrode and a non-alloy drain electrode are formed on the capping layer so as to be spaced from each other.

Field effect transistor having reduced contact resistance and method for fabricating the same

In FET, a second nitride semiconductor layer is provided on a first nitride semiconductor layer, and a source electrode and a drain electrode are each provided to have at least a portion thereof in contact with the second nitride semiconductor layer. A concave portion is formed in the upper surface of the second nitride semiconductor layer to be located between the source electrode and the drain electrode. A gate electrode is provided over the concave portion to cover the opening of the concave portion.

Nitride based semiconductor device with concave gate region

A field effect transistor includes a nitride semiconductor layer; an InAlGaN layer (wherein 0&#x3c;x&#x3c;1, 0&#x3c;y&#x3c;1 and 0&#x3c;x+y&#x3c;1) formed on the nitride semiconductor layer; and a source electrode and a drain electrode formed on and in contact with the InAlGaN layer. The lower ends of the conduction bands of the nitride semiconductor layer and the InAlGaN layer are substantially continuous on the interface therebetween.

Field effect transistor having nitride semiconductor layer

A field effect transistor includes a nitride semiconductor layered structure that is formed on a substrate and includes a capping layer made of a compound represented by a general formula of InAlGaN (wherein 0&#x3c;x&#x2266;1, 0&#x2266;y &#x3c;1 and 0&#x3c;x+y&#x2266;1). A non-alloy source electrode and a non-alloy drain electrode are formed on the capping layer so as to be spaced from each other.

A semiconductor device includes: a first nitride semiconductor layer having at least one projection on an upper surface thereof; a second nitride semiconductor layer formed on a top surface of the projection of the first nitride semiconductor layer and having a higher carrier concentration than the first nitride semiconductor layer; a first electrode formed on the second nitride semiconductor layer so as to overhang like a canopy and functioning as one of a source and a drain; and a second electrode formed to the side of the projection on the first nitride semiconductor layer and functioning as a gate.

Semiconductor device and method for fabricating the same

A nitride semiconductor device includes an active layer including a first nitride semiconductor layer and a second nitride semiconductor layer which are periodically stacked, the second nitride semiconductor layer having a different composition from a composition of the first nitride semiconductor layer. An energy at a lower edge of a conduction band in the first nitride semiconductor layer is lower than an energy at a lower edge of a conduction band in the second nitride semiconductor layer, and an energy at an upper edge of a valence band in the first nitride semiconductor layer is lower than an energy at an upper edge of a valence band in the second nitride semiconductor layer.

Growing community of inventors

Osaka, Japan

Satoshi Nakazawa