Hitachi, Ltd.

Renesas Technology Corp.

Satoshi Iwahashi

Keiichi Higeta

Shigeru Nakahara

Takeshi Suzuki

Kazuo Kanetani

Yoichiro Aihara

The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.

Semiconductor integrated circuit device

Data lines (D, D) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC) coupled to a first comparison data portion (CD) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (), and a third transistor (MC) coupled to a second comparison data line (CD) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.

Semiconductor device

A semiconductor memory device comprises a memory-cell array for storing data, a peripheral circuit for carrying out an operation to read out or write data from or into the memory-cell array, read clock generation circuits (and) each used for generating a read clock signal to be supplied to the peripheral circuit in the operation to read out data from the memory-cell array, write clock generation circuits (and) each used for generating a write clock signal to be supplied to the peripheral circuit in the operation to write data into the memory-cell array. Since the pulse widths of the clock signals in read and writes are adjusted individually, margin insufficiencies of the pulse widths can be evaluated and results of the evaluation can be fed back to a design phase for, among other purposes, correction of a layout.

Semiconductor memory device

The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.

Growing community of inventors

Ome, Japan

Satoshi Iwahashi