Fujitsu Corporation

Fujitsu Semiconductor Limited

Satoru Yoshikawa

Tetsu Tanizawa

Shigenori Ichinose

Tetsuo Kawano

Toshikatsu Hosono

Takashi Yoneda

Yasuo Kamiya

An LSI test apparatus includes a test circuit synthesizing unit that synthesizes a test circuit and inserts the test circuit in a pre-test-synthesis net list; a test pattern generating unit that, based on a post-test-synthesis net list acquired by the test circuit synthesizing unit, generates a test pattern that simultaneously activates selected gated clock buffers; a simulating unit that, using the test pattern generated by the test pattern generating unit, simulates operation of a circuit created from the post-test-synthesis net list; and a power source analyzing unit that analyzes voltage drop in terms of amount, based on operation rate information acquired by the simulating unit.

LSI test apparatus, LSI test method, and computer product

OCV coefficients in a path being an analysis target according to the number of gate stages are calculated in a coefficient arithmetically operating unit by canceling off a variation in delay in each gate in accordance with the number of gate stages in the target path, and timing analysis of the target path is performed in a timing analysis unit by using the OCV coefficient with the number of gate stages being considered, whereby a variation degree in the entire path is reduced in accordance with the number of gate stages in the target path, thus making it possible to carry out accurate timing analysis in consideration of the variation in a chip of a semiconductor integrated circuit.

Semiconductor integrated circuit timing analysis apparatus timing analysis method and timing analysis program

A hold time error list, having for each hold time error path a hold time error value satisfying plural timing constraints, and more specifically a maximum hold time error value for each of timing constraints, as well as a setup time margin map allocating to path a setup time margin satisfying plural timing constraints for each setup time error path, and more specifically minimum value of setup time margins for the same path for each timing constraint, are generated. Also, referring to this setup time margin map, delay buffers, which reduces or eliminates hold time error of hold error list, and a delay of which is within the range of delay amounts and positions equal to or lower than the setup time margin, are inserted. Referring to the setup time margin map, it is possible to insert delay buffer to correct hold time error without causing new setup time errors.

Hold time error correction method and correction program for integrated circuits

A method conducts logic simulation in an integrated circuit device, in which a macro containing logic circuits formed therein is included in a chip including a plurality of cells. The method determines a first delay parameter relating to an input terminal of an internal cell of the macro connected to the input terminal of the macro, and a second delay parameter relating to an output terminal of an internal cell of the macro connected to the output terminal of the macro. The method then determines delay time data for a whole logic circuit including the plurality of cells and the macro, in accordance with delay parameters determined for the macro, in which the first delay parameter is taken as an input terminal delay parameter and the second delay parameter is taken as an output terminal delay parameter; delay parameters determined for the plurality of cells; and connection data for the whole logic circuit. The method merges the determined delay time data for the whole logic circuit and internal delay time data for the macro so as to conduct a logic simulation for the whole logic circuit in accordance with the merged delay time data.

Method of manufacturing integrated circuit device

A method of manufacturing an integration circuit device that includes generating logic library data with respect to a macro that includes a predetermined macro core and boundary cells positioned near input and output terminals of the macro. The logic library data includes delay characteristic data of the boundary cells given as attribute data to the input and output terminals. A logic circuit, that includes a plurality of cells and the macro, is designed, with the cells being connected to the macro core through the boundary cells connected to the input and output terminals. A delay time of the macro is calculated based on the delay characteristic data with respect to the designed logic circuit. A logic simulation on the designed logic circuit is effected based on the calculated delay time.

Large-scale-integration circuit device and method of manufacturing same

A method of verifying integrated circuit operation compares stored data structures which correspond to integrated circuit logic cells. Simulated graph data for a plurality of different types of logic cells are first determined by varying a plurality of factors including: the delay time of a logic cell after a signal is inputted until a signal is outputted, load capacity, and transient time of the inputted signal. The acquired graph data for each of the logic cells is then processed into data having a common origin at a common value and stored into a cell library. The processed graph data is then extracted as general-use graph data by comparing the acquired graph data with one another. A selector selects graph data which corresponds to an object of calculation from the library and an arithmetic logic unit calculates delay time of an actual logic cell based upon the selected graph data.

Growing community of inventors

Kawasaki, Japan

Satoru Yoshikawa