Samsung Electronics Co., Ltd.

Satoru Yamada

Junsoo Kim

Min Hee Cho

Moonyoung Jeong

Dongjin Lee

Hui-Jung Kim

Jae Ho Hong

Kyunghwan Lee

Yongseok Kim

Kyo-Suk Chae

Yoosang Hwang

Bong-Soo Kim

Jaeho Hong

Kyoung-Ho Jung

Yong Kim

Hyuncheol Kim

Kyung Hwan Lee

Sungjin Kim

Jiyoung Kim

Jun Soo Kim

Sungwon Yoo

Wonsok Lee

Ji Eun Lee

Han Jin Lim

Seok Han Park

Sung Heo

Jiho Yoo

Eunae Cho

Young-jin Choi

Gyeongsu Park

Seung-Uk Han

Yongsu Kim

Dong Su Ko

Ki Jae Hur

Kiseok Lee

Dongsoo Woo

Sunghee Han

Hyeongsun Hong

Wook-Je Kim

Chunhyung Chung

Sang-Yeon Han

Kyupil Lee

Honglae Park

Tae Hun Kim

Hyun Uk Park

Young Jin Choi

Jun-Hee Lim

Jun Hee Lim

Hui Jung Kim

Huijung Kim

Sung-Sam Lee

Yoo Sang Hwang

Seunguk Han

Namho Jeon

Seokhan Park

Ji-eun Lee

Moon Young Jeong

Won-Kyung Park

Jin-Seong Lee

Nam-Ho Jeon

Won Sok Lee

Seung Uk Han

Naoto Umezawa

Woo-song Ahn

Nam Ho Jeon

Jun-Su Kim

Woo Song Ahn

Tae Yoon An

Sung Sam Lee

Taek Yong Kim

Min Su Choi

Taehun Kim

Jae-Hoon Lee

Hyun Soo Park

Hyun Wook Park

Joon Soo Han

Min-hee Cho

Jaehoon Lee

Hyuk-Joon Kwon

Junhee Lim

Hyun Cheol Kim

Sung-Ho Jang

Jong-Man Park

Sang-Ho Shin

Sung Won Yoo

Hyoshin Ahn

Cheonan Lee

Young-Jin Choi

Joohyun Jeon

Sungsam Lee

Chang-Hoon Jeon

Si-Ok Sohn

Hae-in Jung

Jung-Bun Lee

Eunae Choi

Shin-Deuk Kim

Hyoung-ho Ko

Ki-Jae Huh

Moon-young Jeong

Sung-Duk Hong

A neuromorphic device includes a synaptic array, including input lines extending in a first direction and receiving input signals independently from axon circuits connected thereto, bit lines extending in a second direction crossing the first direction and outputting output signals, cell strings that each include at least two resistive memristor elements and a string select transistor in series between an input line and a bit line, electrode pads stacked and spaced apart from each other between the input and bit lines and connected to the string select transistor and at least two resistive memristor elements, a decoder to apply a string selection signal or a word line selection signal to the electrode pads, and neuron circuits, each connected to one of the bit lines connected to one of the cell strings, summing the output signals, converting and outputting the summed signal when it is more than a predetermined threshold.

Neuromorphic device and operating method of the same

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes Dand NDin an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and Dis positively-charged deuterium.

Semiconductor devices and methods of manufacturing the same

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate including a trench. The semiconductor device further includes a gate electrode disposed in the trench, and a gate insulating film disposed between the substrate and the gate electrode. The gate electrode includes a gate conductor and a metal element, and an effective work function of the gate electrode is less than an effective work function of the gate conductor.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a first conductive line and a second conductive line spaced apart from the first conductive line. A semiconductor pattern is disposed between the first conductive line and the second conductive line. The semiconductor pattern includes a first semiconductor pattern having first-conductivity-type impurities disposed adjacent to the first conductive line. A second semiconductor pattern having second-conductivity-type impurities is disposed adjacent to the second conductive line. A third semiconductor pattern is disposed between the first semiconductor pattern and the second semiconductor pattern. The third semiconductor pattern includes a first region disposed adjacent to the first semiconductor pattern and a second region disposed between the first region and the second semiconductor pattern. At least one of the first region and the second region comprises an intrinsic semiconductor layer. A first gate line crosses the first region and a second gate line crosses the second region.

Semiconductor devices including semiconductor pattern

A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

Semiconductor device

A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

Semiconductor memory devices

Semiconductor memory devices are provided. A semiconductor memory device includes an isolation layer in a first trench and a first gate electrode portion on the isolation layer. The semiconductor memory device includes a second gate electrode portion in a second trench. In some embodiments, the second gate electrode portion is wider, in a direction, than the first gate electrode portion. Moreover, in some embodiments, an upper region of the second trench is spaced apart from the first trench by a greater distance, in the direction, than a lower region of the second trench. Related methods of forming semiconductor memory devices are also provided.

A semiconductor device includes a stack structure on a substrate, the stack structure including alternating gate electrodes and insulating layers stacked along a first direction, a vertical opening through the stack structure along the first direction, the vertical opening including a channel structure having a semiconductor layer on an inner sidewall of the vertical opening, and a variable resistive material on the semiconductor layer, a vacancy concentration in the variable resistive material varies along its width to have a higher concentration closer to a center of the channel structure than to the semiconductor layer, and an impurity region on the substrate, the semiconductor layer contacting the impurity region at a bottom of the channel structure.

Semiconductor device including data storage structure

Provided is a semiconductor memory device. The semiconductor memory device comprises a first semiconductor pattern including a first impurity region, a second impurity region, and a channel region, the first impurity region spaced apart from a substrate in a first direction and having a first conductivity type, the second impurity region having a second conductivity type different from the first conductivity type, and the channel region between the first impurity region and the second impurity region, a first conductive connection line connected to the first impurity region and extending in a second direction different from the first direction and a first gate structure extending in the first direction and including a first gate electrode and a first gate insulating film, wherein the first gate electrode penetrates the channel region and the first gate insulating film is between the first gate electrode and the semiconductor pattern.

Semiconductor memory device and method for fabricating thereof

A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.

Semiconductor memory device

Memory devices may include a source region, channels, a gate insulation layer pattern, a selection gate pattern, a first gate pattern, a second gate pattern and a drain region. The source region may include first impurities having a first conductivity type at an upper portion of a substrate. The channels may contact the source region. Each of the channels may extend in a vertical direction that is perpendicular to an upper surface of the substrate. The selection gate pattern may be on sidewalls of the channels. The first gate pattern may be on the sidewalls of the channels. The first gate pattern may be a common electrode of all of multiple channels. The second gate patterns may be on the sidewalls of the channels. The drain region may include second impurities having a second conductivity type that is different from the first conductivity type at an upper portion of each of the channels.

Memory devices with vertical channels

A resistive memory device includes a memory cell array, control logic, a voltage generator, and a read-out circuit. The memory cell array includes memory cells connected to bit lines. Each memory cell includes a variable resistance element to store data. The control logic receives a read command and generates a voltage control signal for generating a plurality of read voltages based on the read command. The voltage generator sequentially applies the read voltages to the bit lines based on the voltage control signal. The read-out circuit is connected to the bit lines. The control logic determines values of data stored in the memory cells by controlling the read-out circuit to sequentially compare values of currents sequentially output from the memory cells in response to the plurality of read voltages with a reference current.

Resistive memory device controlling bitline voltage

Growing community of inventors

Yongin-si, South Korea

Satoru Yamada