Sanyo Electric Co., Ltd.

Semiconductor Components Industries, LLC

Sanyo Semiconductor Co., Ltd.

Satoru Shimada

Yoshikazu Yamaoka

Kazunori Fujita

Tomonori Tabe

Seiji Otake

Yasuhiro Takeda

Yoshio Okayama

Shuichi Kikuchi

Toshiyuki Ohkoda

Kazuhiro Sasada

Masaki Hirase

Kazuhiro Yoshitake

Mitsuaki Morigami

Keiichi Ueda

A semiconductor device capable of inhibiting a fabricating process from complication while inhibiting the dielectric strength voltage of a insulating film from reduction is obtained. This semiconductor device includes a groove portion, an insulating film formed on a surface of the groove portion, a gate electrode and a source impurity region, wherein upper ends of the gate electrode, which are portions in contact with the insulating film, are each located at a position identical with or deeper than the range of an impurity introduced from a surface of a semiconductor substrate with respect to the insulating film in order to form the source impurity region and above a lower surface of the source impurity region.

Semiconductor device with insulated gate formed within grooved portion formed therein

The invention provides a trench gate type transistor in which the gate capacitance is reduced, the crystal defect is prevented and the gate breakdown voltage is enhanced. Trenches are formed in an N&#x2212; type semiconductor layer. A uniformly thick silicon oxide film is formed on the bottom of each of the trenches and near the bottom, being round at corner portions. A silicon oxide film is formed on the upper portion of the sidewall of each of the trenches, which is thinner than the silicon oxide film and round at corner portions. Gate electrodes are formed from inside the trenches onto the outside thereof. The thick silicon oxide film reduces the gate capacitance, and the thin silicon oxide film on the upper portion provides good transistor characteristics. Furthermore, with the round corner portions, the crystal defect does not easily occur, and the gate electric field is dispersed to enhance the gate breakdown voltage.

Trench gate type transistor

A method of fabricating a semiconductor device includes a first step of forming a defect suppression film suppressing increase in a defect due to implantation of an impurity on a semiconductor substrate, a second step of forming an active region on a surface of the semiconductor substrate by implanting the impurity through the defect suppression film, a third step of removing the defect suppression film and a fourth step of forming an interface state suppression film suppressing increase in an interface state density of the active region on the active region.

Method of fabricating semiconductor device

The invention provides a trench gate type transistor in which the gate leakage current is prevented and the gate capacitance is reduced. A trench is formed in an N&#x2212; type semiconductor layer. A thin silicon oxide film is formed on a region of the N&#x2212; type semiconductor layer for the active region of the transistor in the trench. On the other hand, a silicon oxide film which is thicker than the silicon oxide film is formed on a region not for the active region. Furthermore, a leading portion extending from inside the trench onto the outside thereof forms a gate electrode contacting the silicon oxide film. This provides a long distance between the gate electrode at the leading portion and the corner portion of the N&#x2212; type semiconductor layer, thereby preventing the gate leakage current and reducing the gate capacitance.

A semiconductor device that reduces the width of an isolation region between semiconductor elements. The semiconductor device includes a semiconductor substrate, an epitaxial layer formed on the semiconductor substrate, a buried layer formed between the semiconductor substrate and the epitaxial layer, a first trench formed in the epitaxial layer so as to surround the buried layer, and an insulation film formed in the first trench.

Semiconductor device

A semiconductor device that suppresses partial discharging to a semiconductor substrate caused by local concentration of current. The semiconductor device includes a semiconductor substrate, a gate electrode buried in the semiconductor substrate, a conductor buried in the semiconductor substrate further inward from the gate electrode, a wiring layer formed in the semiconductor substrate in connection with the conductor, and an insulation film arranged between the gate electrode and the conductor. The conductor is higher than the surface of the semiconductor substrate.

Semiconductor device comprising buried wiring layer

A semiconductor device includes a trench formed in a surface of a semiconductor substrate. A conductor is embedded in the trench. A conductive layer is arranged adjacent to the trench on the surface of the semiconductor substrate. Semiconductor elements, which include sources provided by one of the conductor and the conductive layer and drains provided by the other one of the conductor and the conductive layer, are formed in a semiconductor element formation region. A planar wiring layer is embedded in the semiconductor substrate under the entire semiconductor element formation region and connected to the conductor.

A method for manufacturing a semiconductor substrate including a mask aligning trench. The method includes forming the mask aligning trench and an element partitioning trench. The element partitioning and mask aligning trenches are filled with insulation. The insulation in the element partitioning trench is masked and the insulation in the mask aligning trench is etched. As a result, a residue of the insulation in the mask aligning trench is below the upper edge of the mask aligning trench. The mask aligning trench is easily detected. Thus, positioning a patterning mask on the substrate can be performed accurately.

Semiconductor device and method for manufacturing the same

A method of fabricating a semiconductor device capable of remarkably reducing the quantity of misalignment after an etching step is obtained. This method of fabricating a semiconductor device comprises a first lithography step of transferring a mask pattern onto a first semiconductor substrate as a first resist pattern with positional reference to a first alignment mark, a first etching step of performing etching through the first resist pattern serving as a mask, a step of measuring the quantity of misalignment after the first etching step and a second lithography step of thereafter transferring the mask pattern onto a second semiconductor substrate as a second resist pattern while correcting the positional reference based on the first alignment mark on the basis of the quantity of misalignment after the first etching step. Thus, the positional reference in the second lithography step can be previously corrected to eliminate the quantity of misalignment after the etching step, whereby the quantity of misalignment after the second etching step is remarkably reduced.

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Hashima, Japan

Satoru Shimada