Sumitomo Bakelite Company Limited

International Business Machines Corporation

Disco Corporation

Satoru Katsurayama

Tomoe Yamashiro

Takashi Hirano

Mitsuo Sugino

Jae-Woong Nah

Hiroyuki Yamashita

Tetsuya Miyamoto

Kenzou Maejima

Michael A Gaynes

Richard Francis Indyk

Toru Meura

Yushi Sakamoto

Shigefumi Okada

Toshio Komiyatani

Daisuke Oka

Masaya Koda

Kenzou Mejima

A semiconductor deviceis equipped with a first substrateon which a first semiconductor chipis mounted, a second substrateon which a second semiconductor chipis mounted, and connecting sectionsthat electrically connect the first substrateand the second substrate. The first substratehas build-up layersA andB in each of which an insulating layercontaining a resin and conductor interconnect layersandare laminated alternately, and the respective conductor interconnect layersare connected by a conductive layerprovided in via holes of the insulating layers. The second substratealso has build-up layersA andB. In the insulating layersof the build-up layers in at least one substrate of the first substrateand the second substrate, the average coefficient of thermal expansion of at least one insulating layer along the substrate inplane direction at from 25 degrees centigrade to the glass transition point is 35 ppm/degrees centigrade or less, and the average coefficient of thermal expansion along the substrate thickness direction is 35 ppm/degrees centigrade or less.

Semiconductor device

In one embodiment, a dielectric material layer embedding metal structures is ablated from the chip-containing substrate by laser grooving, which is performed on dicing channels of the chip-containing substrate. Subsequently, an underfill layer is formed over the dielectric material layer in a pattern that excludes the peripheral areas of the chip-containing substrate. The physically exposed dicing channels at the periphery can be employed to align a blade to dice the chip-containing substrate. In another embodiment, an underfill layer is formed prior to any laser grooving. Mechanical cutting of the underfill layer from above dicing channels is followed by laser ablation of the dicing channels and subsequent mechanical cutting to dice a chip-containing substrate.

Wafer dicing employing edge region underfill removal

The problem of the present invention is to provide a chip-on-chip type semiconductor electronic component and a semiconductor device which can meet the requirements for further density increase of semiconductor integrated circuits. The present invention provides: a chip-on-chip type semiconductor electronic component in which a circuit surface of a first semiconductor chip and a circuit surface of a second semiconductor chip are opposed to each other, wherein the distance X between the first semiconductor chip and the second semiconductor chip is 50 &#x3bc;m or less, and the shortest distance Y between the side surface of the second semiconductor chip and the first external electrode is 1 mm or less; and a semiconductor device comprising the same.

Semiconductor electronic component and semiconductor device using the same

The present invention provides an adhesive tape comprising a flux-active compound having a carboxyl group and/or a phenolic hydroxyl group, a thermosetting resin and a film-forming resin. In the adhesive tape of the present invention, the thermosetting resin may be an epoxy resin and may contain a curing agent. The curing agent may be an imidazole compound and/or a phosphorous compound. The adhesive tape of the present invention can be used as an interlayer material for a circuit board and a multilayered flexible printed circuit board.

Adhesive film

Provided is a method for manufacturing an electronic component by using a solder joining method for bonding a first electronic component having a metal electrode with a second electronic component having a solder electrode, the method comprising; (i) forming a resin layer containing a thermosetting resin on at least one of the solder joint surfaces of said first electronic component and said second electronic component; (ii) positioning said metal electrode of said first electronic component and said solder electrode of said second electronic component to face each other, heating said positioned electrodes and applying pressure, and thereby bringing said metal electrode and said solder electrode into contact; (iii) heating electronic components while applying pressure thereby fusion bonding said solder to said metal electrode; and (iv) heating said resin layer.

Method for manufacturing electronic component, and electronic component

The present invention relates to an adhesive tape for electrically connecting semiconductor chips in a chip-on-chip type semiconductor device. The adhesive tape comprising: (A) 10 to 50 wt % of film forming resin; (B) 30 to 80 wt % of curable resin; and (C) 1 to 20 wt % of curing agent having flux activity.

Adhesive tape and semiconductor device using the same

An encapsulation resin composition for preapplication, comprising (a) an epoxy resin, and (b) a curing agent having flux activity, wherein the tack after B-staging is at least 0 gf/5 mm&#x3c6; and at most 5 gf/5 mm&#x3c6;, and the melt viscosity at 130&#xb0; C. is at least 0.01 Pa&#xb7;s and at most 1.0 Pa&#xb7;s; a preapplied encapsulated component and semiconductor device using the composition, and a process of fabrication thereof. The resin composition is less susceptible to air entrapment during provisional placement of semiconductor chips, and excels in workability and reliability.

Encapsulating resin composition for preapplication, semiconductor device made with the same, and process for producing the same

In a method for bonding semiconductor wafers of the present invention, a bonding layer containing a flux-active curing agent and a thermosetting resin is interposed between a first semiconductor wafer and a second semiconductor wafer, thereby producing a semiconductor wafer stacked body in which the first and second semiconductor wafers are stacked together, and then the semiconductor wafer stacked body is compressed in a thickness direction thereof while heating it so that the first and second semiconductor wafers are fixed together by melting and solidifying solder bumps while curing the thermosetting resin, thereby producing a semiconductor wafer bonded body in which first connector portions and second connector portions are electrically connected together through solidified products obtained by melting and solidifying the solder bumps.

Method for bonding semiconductor wafers and method for manufacturing semiconductor device

To prevent formation of entrapped underfill material between solder balls and bonding bumps, fast temperature ramping is employed during a chi assembly after application of an underfill material prior to bonding. Voids formed within the underfill material are subsequently removed by curing the underfill material in a pressurized environment. Temperature cycling on the underfill material is limited during the bonding process in order to maintain viscosity of the underfill material prior to the cure process in the pressurized environment. Further, the underfill material is subjected to the pressurized environment until the cure process is complete to prevent re-formation of voids. The cure process can be a constant temperature or a multi-temperature process including temperature ramping. Further, the cure process can be a constant pressure process or a pressure cycling process that accelerates removal of the voids.

Pressurized underfill cure

An adhesive tapeelectrically connecting conductive components includes a resin layercontaining a thermosetting resin, a solder powderand a curing agent. The solder powderand the curing agent reside in the resin layer, the curing temperature Tof the resin layerand the melting point Tof the solder powdersatisfy T&#x2267;T+20&#xb0; C., wherein the resin layershows a melt viscosity of 50 Pa&#xb7;s or above and 5000 Pa&#xb7;s or below, at the melting point Tof the solder powder

Adhesive tape, connected structure and semiconductor package

A semiconductor device () comprises a first resin substrate () on which a first semiconductor chip () is mounted a surface thereof; a second resin substrate () on which a second semiconductor chip () is mounted on a surface thereof; and a resin base material (), joined to a front surface of the first resin substrate () and to a back surface of the second resin substrate (), so that these surfaces are electrically connected. The resin base material () is disposed in a circumference of the first resin substrate () in the surface of the first resin substrate (). Further, the first semiconductor chip () is disposed in a space section provided among the first resin substrate (), the second resin substrate () and the resin base material () in the surface of the first resin substrate ().

Growing community of inventors

Tokyo, Japan

Satoru Katsurayama