Micron Technology Incorporated

Other

Satish Bedge

Kevin J Torek

Whonchee Lee

Yongjun Jeff Hu

Janos Fucsko

Grady S Waldo

Bob Carstensen

A method of substantially uniformly etching oxides from non-homogeneous substrates is provided. The method utilizes a substantially non-aqueous etchant including an organic solvent and a fluorine-containing compound. The fluorine containing compound may include HF, HF:NHF, (NH)HF, or TMAF:HF and mixtures thereof. The etchant may be applied to chemically non-homogeneous layers such as shallow trench isolation fill oxide layers, or to layers having a non-homogeneous composition or density at different depths within the layers, such as spin-on-glass or spin-on-dielectric films.

Method of substantially uniformly etching non-homogeneous substrates

A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove native oxide at the bottom of the contact with little effect on the BPSG, the contact is dipped in an etch retardant before being dipped in a cleaning solution containing both the etch retardant and an etchant. The dip in etch retardant modifies the surface of the BPSG, thereby lessening the enhanced etching experienced during the initiation of the dip into the etchant/etch retardant cleaning solution. Results of a etchant/etch retardant clean, both with and without the prepassivation, can be illustrated on a graph depicting the change in contact diameter as a function of dip time. Specifically, the results define 'best fit' lines on that graph. For a given dip time, a first line representing the prepassivation+etchant/etch retardant clean is 30 to 40 Angstroms lower than a second line representing the prior art clean using the etchant/etch retardant without prepassivation. Accordingly, the first line's Y-axis intercept, representing the 'zero dip time,' is also 30 to 40 Angstroms lower than the second line's zero dip time.

Passivation for cleaning a material

The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF .

Semiconductor processing methods utilizing low concentrations of reactive etching components

Fabrication techniques for making a semiconductor device. More specifically, techniques for fabricating a wordline in a memory device are provided. Specific heat treatments may be added to the process flow to remove or weaken certain layers formed in the wordlines. For instance, an SiN layer and a crystallized W N layer may form during the fabrication of the wordline. While the layers may provide certain advantages at certain points in the fabrication process, they may be undesirable at subsequent points. One or more anneal processes may be implemented at various points in the processing to eliminate the crystallized W N layer and weaken the SiN layer.

Techniques for improving wordline fabrication of a memory device

Semiconductor processing methods

A contact is defined by an opening etched into borophosphosilicate glass (BPSG) down to a silicon substrate. In a contact cleaning process designed to remove native oxide at the bottom of the contact with little effect on the BPSG, the contact is dipped in an etch retardant before being dipped in a cleaning solution containing both the etch retardant and an etchant. The dip in etch retardant modifies the surface of the BPSG, thereby lessening the enhanced etching experienced during the initiation of the dip into the etchant/etch retardant cleaning solution. Results of a etchant/etch retardant clean, both with and without the prepassivation, can be illustrated on a graph depicting the change in contact diameter as a function of dip time. Specifically, the results define &ldquo;best fit&rdquo; lines on that graph. For a given dip time, a first line representing the prepassivation&plus;etchant/etch retardant clean is 30 to 40 Angstroms lower than a second line representing the prior art clean using the etchant/etch retardant without prepassivation. Accordingly, the first line's Y-axis intercept, representing the &ldquo;zero dip time,&rdquo; is also 30 to 40 Angstroms lower than the second line's zero dip time.

The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching inorganic antireflective layers without etching excessive amounts of an underlying oxide.

Method for selective etching of antireflective coatings

The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of etching inorganic antireflective layers without etching excessive amounts of an underlying oxide. According to one aspect of the present invention, the antireflective layer is selectively etched using an etchant which comprises about 35-40 wt. % NH.sub.4 F and about 0.9-5.0 wt. % H.sub.3 PO.sub.4 in an aqueous solution.

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Boise, ID, United States of America

Satish Bedge