Intel Corporation

Sathya Narasimman Tiagaraj

Gerald S Pasdast

Adel A Elsherbini

Shawna M Liff

Johanna M Swan

Mauro J Kobrinsky

Georgios C Dogiamis

Edward Allyn Burton

William J Lambert

Krishna Bharath

Nicolas Butzen

Vivek Kumar Rajan

Timothy Francis Schmidt

Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

Power delivery through capacitor-dies in a multi-layered microelectronic assembly

An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

Skip level vias in metallization layers for integrated circuit devices

A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.

Dual loop voltage regulator

Growing community of inventors

Chandler, AZ, United States of America

Sathya Narasimman Tiagaraj