Intel Corporation

Sarita Maini

Stephen T Palermo

Abhishek Khade

David Sonnier

William G Burroughs

Shrikant M Shah

Gage Eads

Abhirupa Layek

Bradley Chaddick

Rahul R Shah

Niall D McDonnell

Mrittika Ganguli

Edwin Verplanke

Vasudevan Srinivasan

Lokpraveen B Mosur

Rahul C Shah

Nikhil Gupta

Bruce Richardson

Chetan Hiremath

Christopher MacNamara

John Mangan

Niall Mcdonnell

Praveen Mosur

Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Dynamic load balancing for multi-core computing environments

Methods, apparatus, systems, and articles of manufacture are disclosed for hardware queue scheduling for multi-core computing environments. An example apparatus includes a first core and a second core of a processor, and circuitry in a die of the processor, at least one of the first core or the second core included in the die, the at least one of the first core or the second core separate from the circuitry, the circuitry to enqueue an identifier to a queue implemented with the circuitry, the identifier associated with a data packet, assign the identifier in the queue to a first core of the processor, and in response to an execution of an operation on the data packet with the first core, provide the identifier to the second core to cause the second core to distribute the data packet.

Hardware queue scheduling for multi-core computing environments

Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.

Edge server CPU with dynamic deterministic scaling

Growing community of inventors

Tempe, AZ, United States of America

Sarita Maini