Lam Research Corporation

Saravanapriyan Sriraman

Alex Paterson

Andrew D Bailey, Iii

Alexander Miller Paterson

Mehmet Derya Tetiker

Jon McChesney

Richard Alan Gottscho

Richard A Marsh

John Patrick Holland

Julien Mailfert

Yiting Zhang

Richard Stephan Wise

Harmeet Singh

John Stephen Drewery

Ye Feng

Marcus Musselman

Yan Zhang

Vahid Vahedi

Monica Titus

Thorsten B Lill

Qian Fu

Ying Wu

Zhongkui Tan

Tom A Kamp

Qing Xu

David M Fried

Juline Shoeb

Ricky Marsh

Linda B Braly

A system for performing a bevel cleaning process on a substrate includes a substrate support including an electrode and a plurality of plasma needles arranged around a perimeter of the substrate support. The plasma needles are in fluid communication with a gas delivery system and are configured to supply reactive gases from the gas delivery system to a bevel region of the substrate when the substrate is arranged on the substrate support and electrically couple to the electrode of the substrate support and generate plasma around the bevel region of the substrate.

Semiconductor substrate bevel cleaning

In one embodiment, a plasma processing device may include a dielectric window, a vacuum chamber, an energy source, and at least one air amplifier. The dielectric window may include a plasma exposed surface and an air exposed surface. The vacuum chamber and the plasma exposed surface of the dielectric window can cooperate to enclose a plasma processing gas. The energy source can transmit electromagnetic energy through the dielectric window and form an elevated temperature region in the dielectric window. The at least one air amplifier can be in fluid communication with the dielectric window. The at least one air amplifier can operate at a back pressure of at least about 1 in-HO and can provide at least about 30 cfm of air.

Systems for cooling RF heated chamber components

Computer-implemented methods of optimizing a process simulation model that predicts a result of a semiconductor device fabrication operation to process parameter values characterizing the semiconductor device fabrication operation are disclosed. The methods involve generating cost values using a computationally predicted result of the semiconductor device fabrication operation and a metrology result produced, at least in part, by performing the semiconductor device fabrication operation in a reaction chamber operating under a set of fixed process parameter values. The determination of the parameters of the process simulation model may employ pre-process profiles, via optimization of the resultant post-process profiles of the parameters against profile metrology results. Cost values for, e.g., optical scatterometry, scanning electron microscopy and transmission electron microscopy may be used to guide optimization.

Method of etch model calibration using optical scatterometry

A chamber is provided. The chamber includes a Faraday shield positioned above a substrate support of the chamber. A dielectric window is disposed over the Faraday shield, and the dielectric window has a center opening. A hub having an internal plenum for passing a flow of fluid received from an input conduit and removing the flow of fluid from an output conduit is further provided. The hub has sidewalls and a center cavity inside of the sidewalls for an optical probe, and the internal plenum is disposed in the sidewalls. The hub has an interface surface that is in physical contact with a back side of the Faraday shield. The physical contact provides for a thermal couple to the Faraday shield at a center region around said center opening, and an outer surface of the sidewalls of the hub are disposed within the center opening of the dielectric window.

Air cooled faraday shield and methods for using the same

Computer implemented methods and computer program products have instructions for generating transfer functions that relate segments on lithography photomasks to features produced by photolithography and etching using such segments. Such methods may be characterized by the following elements: (a) receiving after development inspection metrology results produced from one or more first test substrates on which resist was applied and patterned using a set of design layout segments; (b) receiving after etch inspection metrology results produced from one or more second test substrates which were etched after resist was applied and patterned using said set of design layout segments; and (c) generating the transfer function using the set of design layout segments together with corresponding after development inspection metrology results and corresponding after etch inspection metrology results.

Resist and etch modeling

A substrate processing system includes a multi-zone cooling apparatus to provide cooling for all or substantially all of a window in a substrate processing chamber. In one aspect, the apparatus includes one or more plenums to cover all or substantially all of a window in a substrate processing chamber, including under an energy source for transformer coupled plasma in the substrate processing chamber. One or more air amplifiers and accompanying conduits provide air to the one or more plenums to provide air flow to the window. The conduits are connected to plenum inlets at various distances from the center, to direct airflow throughout the window and thus address center hot, middle hot, and edge hot conditions, depending on the processes being carried out in the chamber. In one aspect, the one or more plenums include a central air inlet, to direct air toward the center portion of the window, to address center hot conditions.

Multi-zone cooling of plasma heated window

A substrate processing system for a substrate processing chamber includes a gas delivery system configured to direct process gases toward a substrate support in the substrate processing chamber and a controller. During processing of a substrate arranged on the substrate support the controller is configured to calculate, based on at least one of a position of an edge ring of the substrate support and characteristics of the process gases directed toward the substrate support, a distribution of etch by-product material redeposited onto the substrate during processing and, in response to the calculated distribution, generate control signals to cause an actuator to selectively adjust a position of the edge ring relative to the substrate and cause the gas delivery system to selectively adjust a flow of the process gases.

Control of on-wafer cd uniformity with movable edge ring and gas injection adjustment

The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. Where multiple plasma grids are used, one or more of the grids may be movable, allowing for tenability of the plasma conditions in at least the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber.

Internal plasma grid for semiconductor fabrication

Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

Photoresist design layout pattern proximity correction through fast edge placement error prediction via a physics-based etch profile modeling framework

Layout pattern proximity correction through edge placement error prediction

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Fremont, CA, United States of America

Saravanapriyan Sriraman