International Business Machines Corporation

Globalfoundries U.S. Inc.

Globalfoundries Inc.

Globalfoundries U.S. 2 LLC

Hitachi Chemical Dupont Microsystems, Ltd.

Tessera Intellectual Properties, Inc.

Hitachi Chemicial Dupont Microsystems, L.l.c.

Sarah Huffsmith Knickerbocker

Jonathan H Griffith

Kamalesh K Srivastava

Srinivasa S Reddy

Tien-Jen Cheng

David E Eichstadt

Roger Allan Quon

David R Clarke

Julie C Biggs

John Ulrich Knickerbocker

Govindarajan Natarajan

Jon Alfred Casey

Lester W Herron

John Acocella

Jorge A Lubguban

Kevin Shawn Petrarca

Richard Paul Volant

Cornelia K Tsang

Subhash Laxman Shinde

Shaji Farooq

James N Humenik

Randolph F Knarr

William Edward Sablinski

Robert W Nufer

Mark A Takacs

Steven M Kandetzke

Renuka S Divakaruni

Richard A Bates

Arnold I Baise

Lovell B Wiggins

Daniel P Kirby

Wolfgang Sauter

Paul Stephen Andry

Young-Ho Kim

Thomas M Shaw

George Frederick Walker

Emanuel Israel Cooper

Michael Jay Shapiro

Charles Hampton Perry

Albert M Young

Lawrence D David

Robert Anthony Rita

Rao Venkateswara Vallabhaneni

Christopher Lee Tessler

Ajay Prabhakar Giri

Ananda H Kumar

Jason Lee Frankel

Peter Richard Duncombe

Jae M Park

Jungihl Kim

George Czornyj

Lisa A Fanti

Richard W Adams

Robert R Shaw

Melvin P Zussman

Mark O Neisser

Anthony Mastreani

Peter A Agostino

Kenneth A Bird

Bernard Schwartz

Brent A Anderson

Sampath Purushothaman

Charles Leon Arvin

Bing Dang

Edmund Juris Sprogis

David John Russell

Benjamin V Fasano

Chandrasekhar Narayan

Raschid Jose Bezama

Spyridon Skordas

Sudipta Kumar Ray

Douglas C La Tulipe, Jr

Rosemary A Previti-Kelly

Peter Jeffrey Brofman

Harry David Cox

Kevin R Winstel

Brian Michael Erwin

Donald Rene Wall

Raymond A Jackson

Richard Francis Indyk

Mukta S Farooq

Rebecca D Mih

Joyce C Liu

John Joseph Garant

Srinivasa S N Reddy

Philip L Flaitz

Tracy A Tong

Phillip W Palmatier

Mario E Ecker

Raj N Master

Suresh D Kadakia

Bradley Paul Jones

Lloyd G Burrell

Karen P McLaughlin

Koushik Ramachandran

Vivek M Sura

David H Gabriels

Paul H Palmateer

Sean A Allen

Keith Kwong-Hon Wong

Structures for a photonics chip that include a cavity or groove and methods of forming same. The structure comprises a semiconductor substrate including a first opening, a back-end-of-line stack on the semiconductor substrate, and a dielectric layer on the back-end-of-line stack. The back-end-of-line stack includes a pad, and the dielectric layer includes a second opening that extends to the pad. The structure further comprises an electrical interconnect inside the second opening in the dielectric layer. The electrical interconnect includes a sidewall that is separated in a lateral direction from the dielectric layer by a gap.

Photonics chip patterning with multiple photoresist layers

A bonding structure for a semiconductor substrate and related method are provided. The bonding structure includes a first oxide layer on the semiconductor substrate, and a second oxide layer on the first oxide layer, the second oxide layer for bonding to another structure. The second oxide layer has a higher stress level than the first oxide layer, and the second oxide layer is thinner than the first oxide layer. The second oxide layer may also have a higher density than the first oxide layer. The bonding structure can be used to bond chips to wafer or wafer to wafer and provides a greater bond strength than just a thick oxide layer.

Bonding structure using two oxide layers with different stress levels, and related method

A semiconductor device is provided, which includes a multi-layered substrate having an interposed polymeric film and a device layer arranged over the multi-layered substrate.

Multi-layered substrates of semiconductor devices

An optical system includes a photonics chip, a bridge waveguide structure formed on the chip, and an optical fiber disposed over the chip and optically aligned with the bridge waveguide structure. A cavity between the bridge waveguide structure and the chip is at least partially filled with an adhesive resin and a filler material having a coefficient of thermal expansion (CTE) less than that of the adhesive resin. The filler material may include filler particles dispersed throughout the adhesive resin, or a discrete layer of material separate from the adhesive resin. The composite adhesive material filling the cavity has an effective coefficient of thermal expansion less than the coefficient of thermal expansion of conventional adhesive resins. This lower effective CTE improves the survivability of the overlying bridge waveguide structure following thermal cycling of the optical system.

Fiber alignment to photonics chip

The present disclosure relates to semiconductor structures and, more particularly, to dicing channels used in the singulatation process of interposers and methods of manufacture. The structure includes: one or more redistribution layers; a glass interposer connected to the one or more redistribution layers; a channel formed through the one or more redistribution layers and the glass interposer core, forming a dicing channel; and polymer material conformally filling the channel.

Dicing channels for glass interposers

A semiconductor structures includes a contact fabricated utilizing a multi material trench-layer. The multi material trench layer is utilized to form a contact trench and the contact trench is utilized to form the contact therein. The trench-layer includes a lower barrier trench layer and an upper photoprocessing layer. The photoprocessing layer is utilized pattern and form contact trench. The barrier layer protects an electroplating conductive layer utilized in forming the contact from corrosion that may occur during the removal of the photoprocessing layer.

Dual layer stack for contact formation

A method of forming an integrated circuit assembly includes forming an insulator layer on a preliminary semiconductor assembly. The preliminary semiconductor assembly includes a semiconductor substrate having a first side and a second side opposite the first side, a semiconductor circuitry layer formed on the first side of the semiconductor substrate, and a conductive via extending through the semiconductor substrate from the semiconductor circuitry layer to the second side. The insulator is formed on the second side and an end of the conductive via. The method includes forming a polymer layer on the insulator layer, removing a quantity of the polymer layer sufficient to expose the end of the conductive via through the insulator layer, and forming a conductive contact on the polymer layer and the end of the conductive via.

Integrated circuit assembly with cushion polymer layer

A method of removing a handler wafer. There is provided a handler wafer and a semiconductor device wafer having a plurality of semiconductor devices, the semiconductor device wafer having an active surface side and an inactive surface side. An amorphous carbon layer is applied to a surface of the handler wafer. An adhesive layer is applied to at least one of the amorphous carbon layer of the handler wafer and the active surface side of the semiconductor device wafer. The handler wafer is joined to the semiconductor device wafer through the adhesive layer or layers. Laser radiation is applied to the handler wafer to cause heating of the amorphous carbon layer that in turn causes heating of the adhesive layer or layers. The plurality of semiconductor devices of the semiconductor device wafer are then separated from the handler wafer.

Handler wafer removal facilitated by the addition of an amorphous carbon layer on the handler wafer

Methods and systems for reinforcing the periphery of a semiconductor wafer bonded to a carrier are disclosed. In one embodiment, additional adhesive is applied to the semiconductor wafer prior to bonding. The additional adhesive seeps into a crevice between the carrier and wafer and provides reinforcement. In another embodiment, adhesive is applied to the crevice by a dispenser after the wafer is bonded to the glass carrier.

Reduction of edge chipping during wafer handling

A method of protecting a mold having at least one substantially planar surface provided with a plurality of mold cavities includes inserting a plurality of mandrels into respective ones of the plurality of mold cavities, depositing a layer of mold protection material onto the at least one substantially planar surface and the plurality of mandrels, and removing the plurality of mandrels from the mold substrate.

Protecting a mold having a substantially planar surface provided with a plurality of mold cavities

The process begins with separate device wafers having complimentary chips. Thin metal capture pads, having a preferred thickness of about 10 microns so that substantial pressure may be applied during processing without damaging capture pads, are deposited on both device wafers, which are then tested and mapped for good chip sites. A handle wafer is attached to one device wafer, which can then be thinned to improve via etching and filling. Capture pads are removed and replaced after thinning. The device wafer with handle wafer is diced, and good chips with attached portions of the diced handle wafer are positioned and bonded to the good chip sites of the other device wafer, and the handle wafer portions are removed. The device wafer having known good 3-D chips then undergoes final processing.

Method and structure for optimizing yield of 3-D chip manufacture

A method is provided for making of interconnect solder bumps on a wafer or other electronic device without depositing any significant amount of tin or other solder component from the solder onto the wafer surface which tin can cause shorts or other defects in the wafer. The method is particularly useful for well-known C4NP interconnect technology. In one aspect of the invention, a reducing gas flow rate is used to remove oxides from the solder surfaces and wafer pad surfaces and is of a sufficient determined or pre-determined flow and/or chamber or mold/wafer spacing to provide a gas velocity across the solder surfaces and wafer pad surfaces so that Sn or other contaminants do not deposit on the wafer surface during solder transfer. In another aspect, the transfer contact is performed below the melting point of the solder and subsequently heated to above the melting temperature while in transfer contact. The heated solder in contact with the wafer pads is transferred to the wafer pads.

Process for making interconnect solder Pb-free bumps free from organo-tin/tin deposits on the wafer surface

A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter.

Forming robust solder interconnect structures by reducing effects of seed layer underetching

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Hopewell Junction, NY, United States of America

Sarah Huffsmith Knickerbocker