Kla Tencor Corporation

Kla Corporation

Kla-tencor Technologies Corporation

Santosh Bhattacharyya

Bjorn Brauer

Ashok V Kulkarni

Lisheng Gao

Kris Bhaskar

Hucheng Lee

Saibal Banerjee

Mark Armstrong McCord

Martin Plihal

Richard Wallingford

Brian Duffy

Chris Maher

Ardis Liang

Hubert Altendorfer

Chetana Bhaskar

Kais Maayah

Allen Park

Eliezer Rosengaus

Eugene Shifrin

Hong Chen

Jason Z Lin

Ellis Chang

Robert M Danen

Sangbong Park

Joe Wang

Mohan Mahadevan

Xiaochun Li

Saravanan Paramasivam

Michael John Van Riet

Wei Zhao

Khurram Zafar

Chien-Huei Adam Chen

Erfan Soltanmohammadi

Raghav Babulnath

Aneesh Khullar

Ge Cong

Gordon Rouse

Thirupurasundari Jayaraman

Cecelia Anne Campochiaro

Jagdish Chandra Saraswatula

Raghavan Konuru

Philip Measor

Christopher Maher

Srikanth Kandukuri

Bryant Mantiply

Christophe Fouquet

Mike Van Riet

Jacob George

Ashok Mathew

Gangadharan Sivaraman

Rahul Lakhawat

Boshi Huang

Igor N Germanenko

Bo Hua

Pavan Kumar

Benjamin Murray

Lalita A Balasubramanian

Karthikeyan Subramanian

Sanbong Park

Devashish Sharma

Evgeni Shifrin

Lian Yao

Da Chen

Alpa Kohli

Bjorn Braeuer

Tarunark Singh

David Dowling

Lalita Balasubramanian

A rendered image is aligned with a scanning electron microscope (SEM) image to produce an aligned rendered image. A reference image is aligned with the SEM image to produce an aligned reference image. A threshold probability map also is generated. Dynamic compensation of the SEM image and aligned reference image can produce a corrected SEM image and corrected reference image. A thresholded defect map can be generated and the defects of the thresholded probability map and the signal-to-noise-ratio defects of the thresholded defect map are filtered using a broadband-plasma-based property to produce defect-of-interest clusters.

BBP assisted defect detection flow for SEM images

A system for defect review and classification is disclosed. The system may include a controller, wherein the controller may be configured to receive one or more training images of a specimen. The one or more training images including a plurality of training defects. The controller may be further configured to apply a plurality of difference filters to the one or more training images, and receive a signal indicative of a classification of a difference filter effectiveness metric for at least a portion of the plurality of difference filters. The controller may be further configured to generate a deep learning network classifier based on the received classification and the attributes of the plurality of training defects. The controller may be further configured to extract convolution layer filters of the deep learning network classifier, and generate one or more difference filter recipes based on the extracted convolution layer filters.

System and method for difference filter and aperture selection using shallow deep learning

Methods and systems for discovery of defects of interest (DOI) buried within three dimensional semiconductor structures and recipe optimization are described herein. The volume of a semiconductor wafer subject to defect discovery and verification is reduced by storing images associated with a subset of the total depth of the semiconductor structures under measurement. Image patches associated with defect locations at one or more focus planes or focus ranges are recorded. The number of optical modes under consideration is reduced based on any of a comparison of one or more measured wafer level defect signatures and one or more expected wafer level defect signatures, measured defect signal to noise ratio, and defects verified without de-processing. Furthermore, verified defects and recorded images are employed to train a nuisance filter and optimize the measurement recipe. The trained nuisance filter is applied to defect images to select the optimal optical mode for production.

Defect discovery and recipe optimization for inspection of three-dimensional semiconductor structures

A method of semiconductor-wafer image alignment is performed at a semiconductor-wafer defect-inspection system. In the method, a semiconductor wafer is loaded into the semiconductor-wafer defect-inspection system. Pre-inspection alignment is performed for the semiconductor wafer. After performing the pre-inspection alignment, a first swath is executed to generate a first image of a first region on the semiconductor wafer. An offset of a target structure in the first image with respect to a known point is determined. Defect identification is performed for the first image, using the offset. After executing the first swath and determining the offset, a second swath is executed to generate a second image of a second region on the semiconductor wafer. While executing the second swath, run-time alignment of the semiconductor wafer is performed using the offset.

Defect-location determination using correction loop for pixel alignment

Methods and systems for setting up inspection of a specimen with design and noise based care areas are provided. One system includes one or more computer subsystems configured for generating a design-based care area for a specimen. The computer subsystem(s) are also configured for determining one or more output attributes for multiple instances of the care area on the specimen, and the one or more output attributes are determined from output generated by an output acquisition subsystem for the multiple instances. The computer subsystem(s) are further configured for separating the multiple instances of the care area on the specimen into different care area sub-groups such that the different care area sub-groups have statistically different values of the output attribute(s) and selecting a parameter of an inspection recipe for the specimen based on the different care area sub-groups.

And noise based care areas

Systems and methods for detecting defects on a reticle are provided. One system includes computer subsystem(s) that include one or more image processing components that acquire images generated by an inspection subsystem for a wafer, a main user interface component that provides information generated for the wafer and the reticle to a user and receives instructions from the user, and an interface component that provides an interface between the one or more image processing components and the main user interface. Unlike currently used systems, the one or more image processing components are configured for performing repeater defect detection by applying a repeater defect detection algorithm to the images acquired by the one or more image processing components, and the repeater defect detection algorithm is configured to detect defects on the wafer using a hot threshold and to identify the defects that are repeater defects.

High sensitivity repeater defect detection

A system, method, and computer program product are provided for automatically generating a wafer image to design coordinate mapping. In use, a design of a wafer is received by a computer processor. In addition, an image of a wafer fabricated from the design is received by the computer processor. Further, a coordinate mapping between the design and the image is automatically generated by the computer processor.

System, method and computer program product for automatically generating a wafer image to design coordinate mapping

Defect detection is performed by comparing a test image and a reference image with a rendered design image, which may be generated from a design file. This may occur because a comparison of the test image and another reference image was inconclusive due to noise. The results of the two comparisons with the rendered design image can indicate whether a defect is present in the test image.

Combined patch and design-based defect detection

Methods and systems for detecting defects on a specimen are provided. One method includes identifying first and second portions of dies on a specimen as edge dies and center dies, respectively. The method also includes determining first and second inspection methods for the first and second portions, respectively. Parameter(s) of comparisons performed in the first and second inspection methods are different. The method further includes detecting defects in at least one of the edge dies using the first inspection method and detecting defects in at least one of the center dies using the second inspection method.

Inspection for specimens with extensive die to die process variation

Criticality of a detected defect can be determined based on context codes. The context codes can be generated for a region, each of which may be part of a die. Noise levels can be used to group context codes. The context codes can be used to automatically classify a range of design contexts present on a die without needing certain information a priori.

Defect sensitivity of semiconductor wafer inspectors using design data with wafer image data

Methods and systems for determining a position of output generated by an inspection subsystem in design data space are provided. In general, some embodiments described herein are configured for substantially accurately aligning inspection subsystem output generated for a specimen to a design for the specimen despite deformation of the design in the inspection subsystem output. In addition, some embodiments are configured for generating and/or using alignment targets that can be shared across multiple specimens of the same layer and design rule for alignment of inspection subsystem output generated for a specimen to a design for the specimen.

Sub-pixel alignment of inspection to design

Shape primitives are used for inspection of a semiconductor wafer or other workpiece. The shape primitives can define local topological and geometric properties of a design. One or more rules are applied to the shape primitives. The rules can indicate presence of a defect or the likelihood of a defect being present. A rule execution engine can search for an occurrence of the shape primitives covered by the at least one rule.

Shape based grouping

Methods and systems for determining a position of output generated by an inspection subsystem in design data space are provided. One method includes selecting one or more alignment targets from a design for a specimen. At least a portion of the one or more alignment targets include built in targets included in the design for a purpose other than alignment of inspection results to design data space. At least the portion of the one or more alignment targets does not include one or more individual device features. One or more images for the alignment target(s) and output generated by the inspection subsystem at the position(s) of the alignment target(s) may then be used to determine design data space positions of other output generated by the inspection subsystem in a variety of ways described herein.

Alignment of inspection to design using built in targets

Methods and systems for determining design coordinates for defects detected on a wafer are provided. One method includes aligning a design for a wafer to defect review tool images for defects detected in multiple swaths on the wafer by an inspection tool, determining a position of each of the defects in design coordinates based on results of the aligning, separately determining a defect position offset for each of the multiple swaths based on the swath in which each of the defects was detected (swath correction factor), the design coordinates for each of the defects, and a position for each of the defects determined by the inspection tool, and determining design coordinates for the other defects detected in the multiple swaths by the inspection tool by applying the appropriate swath correction factor to those defects.

Determining design coordinates for wafer defects

Methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer are provided. One computer-implemented method for generating a standard reference die for use in a die to standard reference die inspection includes acquiring output of an inspection system for a centrally located die on a wafer and one or more dies located on the wafer. The method also includes combining the output for the centrally located die and the one or more dies based on within die positions of the output. In addition, the method includes generating the standard reference die based on results of the combining step.

Methods for generating a standard reference die for use in a die to standard reference die inspection and methods for inspecting a wafer

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San Jose, CA, United States of America

Santosh Bhattacharyya