Intel Corporation

Sanka Ganesan

Robert L Sankman

Debendra Mallik

Ram S Viswanath

Shawna M Liff

Omkar G Karhade

Rajasekaran Swaminathan

Sri Chaitra Jyotsna Chavali

Zhiguo Qian

Zhichao Zhang

Xavier Francois Brun

Kemal Aygun

William J Lambert

Mitul Bharat Modi

Manish Dubey

Ravindranath Vithal Mahajan

Robert Alan May

Robert M Nickerson

Tarek A Ibrahim

Jason M Gamba

Nitesh Nimkar

Krishna Srinivasan

Zhaohui Zhu

Wilfred Gomes

Amruthavalli Pallavi Alur

Michael J Hill

Bassam Mohammed Ziadeh

Sri Chaitra J Chavali

Aastha Uppal

Zhenguo Jiang

Kevin T McCarthy

Chandrashekhar Ramaswamy

Leigh M Tribolet

Aleksandar Aleksov

Thorsten Meyer

Henning Braunisch

John Stephen Guzek

Nitin A Deshpande

Eric Jin Li

Jeffory L Smalley

Charan K Gurumurthy

Donald Tiendung Tran

Edvin Cetegen

Doug B Ingerly

Yidnekachew S Mekonnen

Jimin Yao

Gregorio R Murtagian

Mark S Hlad

Jeff C Morriss

David J Llapitan

Yiqun Bai

Vipul V Mehta

Eric C Palmer

Eduard Roytman

Zhaozhi Li

Abhishek A Sharma

Mark T Bohr

Mauro J Kobrinsky

George Vergis

Mathew J Manusharow

Bernd Waidhas

Kaladhar Radhakrishnan

Xiang Li

James Chris Matayabas, Jr

Yoshihiro Tomita

Gerald Ofner

Thomas Wagner

Leonel R Arana

Joshua Heppner

Je-Young Chang

Yikang Deng

Klaus Reingruber

Kevin Fischer

Sriram Srinivasan

Richard J Dischler

Gaurav Chawla

Dimitrios Ziakas

Bassam N Coury

Gary Baxter Long

Kuang C Liu

Timothy D Wig

Weihua Tang

Bharat P Penmecha

Mohiuddin M Mazumder

Vijaykumar Krithivasan

Chong J Zhao

Yosuke Kanaoka

Jonathan W Thibado

Lizabeth Keser

Yu Zhang

Mani Prakash

John M Lynch

Neal E Ulen

Yu Amos Zhang

Todd A Hinck

Anne Augustine

Cemil S Geyik

Timothy M Swettlen

Arghya Sain

Pilin Liu

Ultra-thin, hyper-density semiconductor packages and techniques of forming such packages are described. An exemplary semiconductor package is formed with one or more of: (i) metal pillars having an ultra-fine pitch (e.g., a pitch that is greater than or equal to 150 μm, etc.); (ii) a large die-to-package ratio (e.g., a ratio that is equal to or greater than 0.85, etc.); and (iii) a thin pitch translation interposer. Another exemplary semiconductor package is formed using coreless substrate technology, die back metallization, and low temperature solder technology for ball grid array (BGA) metallurgy. Other embodiments are described.

Ultra-thin, hyper-density semiconductor packages

Generally discussed herein are systems, methods, and apparatuses that include conductive pillars that are about co-planar. According to an example, a technique can include growing conductive pillars on respective exposed landing pads of a substrate, situating molding material around and on the grown conductive pillars, removing, simultaneously, a portion of the grown conductive pillars and the molding material to make the grown conductive pillars and the molding material about planar, and electrically coupling a die to the conductive pillars.

Planar integrated circuit package interconnects

An example microelectronic assembly comprises a support structure; an interposer above the support structure; a first die in the interposer, the first die including through-substrate vias (TSVs); and a second die in the interposer, the second die lacking TSVs. A die-to-package support (DTPS) interconnect field on a first face of the first die is substantially identical to a DTPS interconnect field on a first face of the second die, the DTP interconnect fields comprising a plurality of DTPS interconnects for connecting the first and second dies to the support structure. A die-to-die (DTD) interconnect field on a second face of the first die is substantially identical to a DTD interconnect field on a second face of the second die, the DTD interconnect fields comprising a plurality of DTD interconnects.

Low cost embedded integrated circuit dies

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first redistribution layer (RDL), having a first surface with first conductive contacts having a first pitch between 170 microns and 400 microns, an opposing second surface, and first conductive pathways between the first and second surfaces; a first die and a conductive pillar in a first layer on the first RDL; a second RDL on the first layer, the second RDL having a first surface, an opposing second surface with second conductive contacts having a second pitch between 18 microns and 150 microns, and second conductive pathways between the first and second surfaces; and a second die, in a second layer on the second RDL, electrically coupled to the first conductive contacts via the first conductive pathways, the conductive pillar, the second conductive pathways, and the second conductive contacts.

Microelectronic assemblies with direct attach to circuit boards

An inductor can be formed in a coreless electronic substrate, such that the fabrication process does not result in the magnetic material used in the inductor leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming conductive vias with a lithographic process, rather than a standard laser process, in combination with panel planarization to prevent exposure of the magnetic material to the plating and/or etching solutions/chemistries.

Coreless electronic substrates having embedded inductors

Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate. The semiconductor package further includes a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die. The semiconductor package further includes a power source coupled to the through silicon via, a first electronic component electronically coupled to the bridge die, and a second electronic component electronically coupled to the bridge die. The semiconductor package further includes an overmold at least partially encasing the first electronic component, second electronic component, and the bridge die.

Embedded die architecture and method of making

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

Microelectronic component having molded regions with through-mold vias

Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

Integrated circuit assemblies with direct chip attach to circuit boards

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

Multi-die ultrafine pitch patch architecture of interconnect bridge over glass layer and method of making

Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.

Package on active silicon semiconductor packages

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.

Scalable high speed high bandwidth IO signaling package architecture and method of making

Disclosed herein are integrated circuit (IC) structures that may be included in package substrates. For example, disclosed herein are passive components in package substrate, wherein the passive components include at least one non-circular via and at least one pad in contact with the at least one non-circular via, and the passive components include an inductor or a capacitor. Other embodiments are also disclosed.

Integrated circuit structures in package substrates

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.

Ultrathin bridge and multi-die ultrafine pitch patch architecture and method of making

Growing community of inventors

Chandler, AZ, United States of America

Sanka Ganesan