Intel Corporation

Other

Tahoe Research, Ltd.

Sanjeev S Jahagirdar

Altug Koker

Joydeep Ray

Abhishek R Appu

Varghese George

Balaji Vembu

Vasanth Ranganathan

Kamal Sinha

Inder M Sodhi

Subramaniam M Maiyuran

Jose P Allarey

Prasoonkumar Surti

Eriko Nurvitadhi

Nicolas C Galoppo Von Borries

Kiran Chand Veernapu

Anbang Yao

Nikos Kaburlasos

Xiaoming Chen

Elmoustapha Ould-Ahmed-Vall

Tatiana Shpeisman

Ping Tak Tang

Michael S Strickland

Linda L Hurd

Rajkishore Barik

Dukhwan Kim

Tsung-Han Lin

Josh B Mastronarde

Ryan Donovan Wells

Stephen Anthony Fischer

John Charles Weast

Lakshminarayanan Striramassarma

Iqbal Rajwani

Stephen H Gunther

Travis T Schluessler

Narayan Srinivasa

Feng Chen

Alon Naveh

Nadathur Rajagopalan Satish

Mike B Macpherson

Farshad Akhbari

Sanu K Mathew

Mark A Anders

Himanshu Kaul

Vikranth Vemulapalli

Shai Rotem

Liwei Ma

Justin E Gottschlich

Sara S Baghsorkhi

Chandrasekaran Sakthivel

Bhushan M Borole

Ken Drottar

Peter L Doyle

John H Feit

Devan Burke

Jacek Kwiatkowski

Philip R Laws

Ashish V Choubal

Satish K Damaraju

Scott R Janus

Jeremy J Shrall

Xinmin Tian

Brent E Insko

Guei-Yuan Lueh

Anupama Ambardar Thaploo

Kai Xiao

Ben J Ashbaugh

David M Puffer

Narayan Biswal

Aravindh V Anantaraman

Stanley J Baran

Abhishek Venkatesh

Pattabhiraman K

Wenyin Fu

Deborah T Marr

Gokcen Cilingir

Valentin Andrei

Nilesh V Shah

Tomasz Janczak

Barnan Das

Sungye Kim

Archie Sharma

Mayuresh M Varerkar

Nicholas J Adams

Daniel J Ragland

Lidong Xu

Eric C Samson

James M Holland

Eric J Hoekstra

Efraim Rotem

Ankur N Shah

Changliang Wang

Mike MacPherson

Jonathan Kennedy

Achmed Rumi Zahir

Michael T Klinglesmith

Chandra S Gurram

Kevin Nealis

Anant S Deval

Zeev Offen

Michael Zelikson

A mechanism is described for detecting, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network, analyzing the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks, configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks, and monitoring utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjusting allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.

Coordination and increased utilization of graphics processors during inference

In accordance with some embodiments, the render rate is varied across and/or up and down the display screen. This may be done based on where the user is looking in order to reduce power consumption and/or increase performance. Specifically the screen display is separated into regions, such as quadrants. Each of these regions is rendered at a rate determined by at least one of what the user is currently looking at, what the user has looked at in the past and/or what it is predicted that the user will look at next. Areas of less focus may be rendered at a lower rate, reducing power consumption in some embodiments.

Regional adjustment of render rate

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Instructions and logic to perform floating point and integer operations for machine learning

A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

Efficient thread group scheduling

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

Systems and methods for cache optimization

Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Systems and methods for error detection and control for embedded memory and compute elements

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, cache or DRAM memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

Enabling product SKUs based on chiplet configurations

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

Disaggregation of system-on-chip (SOC) architecture

Systems and methods for cache utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

Growing community of inventors

Folsom, CA, United States of America

Sanjeev S Jahagirdar