International Business Machines Corporation

International Business Corporation

Sanjeev Balwant Sathe

David James Alcoe

William Louis Brodsky

Glenn L Kehley

Voya Rista Markovich

George Henry Thiel

William Infantolino

Varaprasad Venkata Calmidi

John R Slack

Bahgat Ghaleb Sammakia

Anthony P Ingraham

Krishna Darbha

Seungbae Park

Li Li

Charles Gerard Woychik

Miguel Angel Jimarez

David V Caletka

Randall Joseph Stutzman

Steven G Rosser

Pratap Singh

Matthew M Reiss

Kishor V Desai

Eric A Johnson

Sandeep B Sane

Jamil A Wakil

Anandaroop Bhattacharya

Aleksander Zubelewicz

Peter A Moschak

Maganlal S Patel

A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.

Wafer scale thin film package

An electronic package having one or more components comprising: a substrate having a first coefficient of thermal expansion; a lid attached to the substrate, the lid including a vapor chamber, the lid having a second coefficient of thermal expansion, the first coefficient of thermal expansion matched to the second coefficient of expansion; a thermal transfer medium in contact with a back surface of each component and an outer surface of a lower wall of the lid; and each component electrically connected to a top surface of the substrate.

Thermally enhanced lid for multichip modules

Removing heat generated by an operating IC chip from both the chip and the electronics package containing the chip is essential for proper system operation and to increase the life of the electronics package. Using an air permeable lid with the electronic package increases the heat transfer away from the IC chip and electronics package, thereby cooling the chip and the package.

Electronic package with thermally-enhanced lid

A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or 'domed' back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.

Non-planar surface for semiconductor chips

An electronic packaging structure and method of forming thereof wherein the structure is constituted of a modular arrangement which reduces stresses generated in a chip, underfill, and ball grid array connection with a flexible substrate in the form of an organic material, which stresses may result in potential delamination due to thermally-induced warpage between the components of the modular arrangement.

Method and packaging structure for optimizing warpage of flip chip organic packages

An electronic package and method of making same in which a circuitized substrate having a first stiffness includes a plurality of electrically conductive circuit members on a first portion of the circuitized substrate and is adapted for having solder connections thereon and for being electrically connected to a semiconductor chip. A stiffener layer having a second stiffness is positioned on a second portion of the circuitized substrate relative to the first portion, the second stiffness of the stiffener layer distributing a portion of the first stiffness of said circuitized substrate so as to substantially prevent failure of the solder connections between the electrically conductive circuit members and the semiconductor chip during operation of the electronic package.

Electronic package having a thermal stretching layer

A method and structure to electrically couple a semiconductor device to a substrate that is divided into a plurality of segments. Alternatively, a semiconductor device may be divided into a plurality of segments and the plurality of segments are electrically coupled to a single substrate.

Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers

A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.

Wafer with semiconductor chips mounted thereon

A method and an article made by a method for embedding optical fibers into an organic laminate structure. The optical fiber cabling, along with its cladding, is placed upon a first laminate layer that includes a composite made of silica fillers and a frictionless material such as polytetrafluoroethylene (PTFE). Then a second layer of PTFE material with silica fillers and copper sheeting is placed on top of the PTFE with silica fillers composite. The PTFE material with silica fillers flows about the optical fibers at a temperature approximately fifty degrees above the PTFE with silica fillers material's melting point. This procedure completely encases the optical fibers within an opaque sheath.

Laminate substrate containing fiber optic cables

Semiconductor chip module and method of manufacture of same

A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or &ldquo;domed&rdquo; back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.

Stress reduction in flip-chip PBGA packaging by utilizing segmented chip carries

Growing community of inventors

Binghamton, NY, United States of America

Sanjeev Balwant Sathe