Applied Materials, Inc.

Intel Corporation

Micro Materials Inc.

Sanjay S Natarajan

Gaurav Thareja

Gill Yong Lee

Sung-Kwan Kang

Priyadarshi Panda

Suketu Arun Parikh

Regina Germanie Freed

Abhijit Basu Mallick

Srinivas Gandikota

Susmit Singha Roy

Abhishek Dube

Benjamin Colombeau

Mukund Srinivasan

Patricia M Liu

Tomohiko Kitajima

Jianxin Lei

Uday Mitra

Chang Seok Kang

Lequn Liu

Keyvan Kashefizadeh

Nitin K Ingle

Anchuan Wang

Stephen M Cea

Seshadri Ganguli

Rui Cheng

Xikun Wang

Yi-Chiau Huang

Sang Ho Yu

Xuebin Li

Sean W King

Swaminathan T Srinivasan

Sean M Seutter

Ho-yung David Hwang

Saurabh Chopra

Sunit Tyagi

Ramune Nagisetty

Tushar Mandrekar

Nobuyuki Sasaki

Myungsun Kim

Jorge Pablo Fernandez

Ravindra Soman

Michael Anthony Stolfi

Andy Lo

In Seok Hwang

Dong Wu

Rajib Lochan Swain

Khaled A Elamrawi

Ning Li

Ying Di Zhang

Mark T Bohr

Shashank Sharma

Xianmin Tang

Bernhard Sell

Mihaela A Balseanu

Avgerinos V Gelatos

Zhebo Chen

Jingmei Liang

Martin Jay Seamons

Ibrahim Ban

Kevin Fischer

Takashi Kuratomi

Matthias Bauer

Madhur Sachan

Wenting Hou

Dimitri R Kioussis

Michael A Childs

Shuchi Sunil Ojha

Tom S Choi

Yuriy Shusterman

A substrate processing method includes creating a mask on a top surface of a workpiece. A first portion of a gap fill material is overlaid by the mask and a second portion of the gap fill material is exposed through an opening in the mask. The method further includes exposing the workpiece to a plasma. The method further includes performing a first etching of the first portion of the gap fill material to create a first cavity while the second portion of the gap fill material remains in place, depositing a first metal-containing substance in the first cavity, performing a second etching of the second portion of the gap fill material to create a second cavity while the first metal-containing substance remains in place, and depositing a second metal-containing substance in the second cavity.

Multi color stack for self aligned dual pattern formation for multi purpose device structures

Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

Selective silicon etch for gate all around transistors

Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

3D DRAM structure with high mobility channel

Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.

Conformal high concentration boron doping of semiconductors

Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.

Stacked transistor device

Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

Method of testing a gap fill for DRAM

A semiconductor device fabrication process includes forming gates on a substrate having a plurality of openings, each gate having a conducting layer a first metal and a gate dielectric layer of a first dielectric material, partially filling the openings with a second dielectric material, forming a first structure on the substrate in a processing system without breaking vacuum, depositing a third dielectric material over the first structure, and forming a planarized surface of the gates and a surface of the third dielectric material that is disposed over the first structure. The forming of the first structure includes forming trenches by removing second portions of the second dielectric material within each opening, forming recessed active regions in the trenches by partially filling the trenches with a second metal, forming a liner over each recessed active region, and forming a metal cap layer over each liner.

Gate contact over active regions

Methods of forming and processing semiconductor devices which utilize a three-color process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing the formation of self-aligned growth pillars. The pillars lead to taller gate heights and increased margins against shorting defects.

Self-aligned contact and contact over active gate structures

A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

Integrated CMOS source drain formation with advanced control

3D dram structure with high mobility channel

Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

Method of fabricating a semiconductor device having reduced contact resistance

Methods of manufacturing memory devices are provided. The methods decrease the thickness of the first layers and increase the thickness of the second layers. Semiconductor devices are described having a film stack comprising alternating nitride and second layers in a first portion of the device, the alternating nitride and second layers of the film stack having a nitride:oxide thickness ratio (N:O); and a memory stack comprising alternating word line and second layers in a second portion of the device, the alternating word line and second layers of the memory stack having a word line:oxide thickness ratio (W:O), wherein 0.1(W:O)&#x3c;N:O&#x3c;0.95(W:O).

3D-NAND mold

Growing community of inventors

Hillsboro, OR, United States of America

Sanjay S Natarajan