Advanced Micro Devices Corporation

Lsi Logic Corporation

Vlsi Technology, Inc.

Vsli Technology, Inc.

Sanjay Dandia

Stephen F Heng

Mahesh S Hardikar

Ali Hassanzadeh

Thomas P Dolbear

Daniel Cavasin

Chia-Ken Leong

Jayarama N Shenoy

Michael J Steidl

Nikon Banouvong

Gerald Robert Talbot

Tai-Yu Chou

Aydin Koc

ChangWei Liang

A method for dimensioning a land grid array pad can include forming an initial landing area of a land grid array pad, wherein the initial landing area is dimensioned to cause at least a majority of a landing surface of one or more socket pins to land off of the initial landing area prior to actuation of one or more sockets including the one or more socket pins. The method can also include forming a final landing area of the land grid array pad, wherein the final landing area is dimensioned to maintain electrical contact with the landing surface of the one or more socket pins after actuation of the one or more sockets including the one or more socket pins. Various other methods and systems are also disclosed.

Systems and methods for dimensioning a land grid array pad

An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin. An indium preform is placed between the second adhesion layer and the lid and the indium preform is reflowed.

Back side metallization

An integrated circuit assembly includes an integrated circuit package substrate and a conductive land pad disposed on a surface of the integrated circuit package substrate. The conductive land pad comprises a conductor portion, an isolated conductor portion, and an isolation portion disposed between the conductor portion and the isolated conductor portion. The isolated conductor portion may surround a first side of the conductor portion and a second side of the conductor portion. The isolated conductor portion may surround a portion of a perimeter of the conductor portion. The isolation portion may include a gap between the conductor portion and the isolated conductor portion. The gap may have a width smaller than a radius of an interconnect structure of a receiving structure.

Land pad design for high speed terminals

An integrated circuit device wafer includes a silicon wafer substrate and a back side metallization structure. The back side metallization structure includes a first adhesion layer on the back side of the substrate, a first metal later over the first adhesion layer, a second metal layer over the first metal layer, and a second adhesion layer over the second metal layer. The first includes at least one of: silicon nitride and silicon dioxide. The first metal layer includes titanium. The second metal layer includes nickel. The second adhesion layer includes at least one of: silver, gold, and tin.

Various apparatus and methods of electrically connecting a packaged integrated circuit to a circuit board are disclosed. In one aspect, an apparatus includes a first frame to be mounted on the circuit board and having a first end. An insulating housing is adapted to be mounted on the circuit board and positioned in the first frame. A second frame is pivotally coupled to the first frame. The second frame includes two spaced-apart rail members and a cross member coupled to and between the rail members opposite the first end of the second frame. The rail members are operable to receive the packaged integrated circuit. The second frame has at least one engagement member to engage a first portion of the insulating housing when the second frame is pivoted toward the insulating housing. A third frame is pivotally coupled to the first frame to apply force to the packaged integrated circuit.

Circuit board socket with rail frame

Various semiconductor chip packages and methods of assembling and making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a stiffener frame to a first side of a substrate. The stiffener frame has a central opening to accommodate a semiconductor chip and an outer edge surface. A semiconductor chip is coupled to the first side in the opening. A lid is coupled to the stiffener frame with an adhesive. The lid has a first edge surface set back from the outer edge surface of the stiffener frame. The adhesive is set back from the outer edge surface of the stiffener frame.

Growing community of inventors

San Jose, CA, United States of America

Sanjay Dandia