Freescale Semiconductor,inc.

Yonsei University

Sangwoo Lim

Paul Grudowski

Robert F Steimle

Hsing H Tseng

Choh-Fei Yeap

Olubunmi O Adetutu

Venkat Kolagunta

Laegu Kang

Tien Ying Luo

Yongjoo Jeon

Mohamad M Jahanbani

Geoffrey (Choh-Fei) Yeap

Changjin Son

Stanley L Filipiak

A non-phosphoric acid-based silicon nitride film etching composition includes 5 to 50 wt % of an organic acid-based chelating agent including an organic phosphonic acid group, a carboxylic acid group, or a combination thereof, based on a total weight of the etching composition. The etching composition for pressurization suppresses etching a silicon oxide film and selectively etches a silicon nitride film in a vertically laminated structure in which both the silicon nitride film and the silicon oxide film are exposed to a surface or the silicon nitride film and the silicon oxide film are alternately laminated.

Non-phosphoric acid-based silicon nitride film etching composition and etching method using the same

A semiconductor device includes a substrate (), a first insulating layer () over a surface of the substrate (), a layer of nanocrystals () over a surface of the first insulating layer (), a second insulating layer () over the layer of nanocrystals (). A nitriding ambient is applied to the second insulating layer () to form a barrier to further oxidation when a third insulating layer () is formed over the substrate (). The nitridation of the second insulating layer () prevents oxidation or shrinkage of the nanocrystals and an increase in the thickness of the first insulating layerwithout adding complexity to the process flow for manufacturing the semiconductor device ().

Semiconductor device having nitridated oxide layer and method therefor

An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure including a second gate electrode surrounding a second sidewall spacer having second stress. The first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode and the second sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode, wherein the first stress has a lower value as compared to the second stress. More than one process can be used to form the electronic device.

Process for forming an electronic device including transistor structures with sidewall spacers

A gate dielectric is treated with a nitridation step and an anneal. After this, an additional nitridation step and anneal is performed. The second nitridation and anneal results in an improvement in the relationship between gate leakage current density and current drive of the transistors that are ultimately formed.

Method of making a nitrided gate dielectric

A method of forming an electronic device includes etching a portion of a first gate dielectric layer to reduce a thickness of the gate dielectric layer within that portion. In one embodiment, portions not being etched may be covered by mask. In another embodiment, different portions may be etched during different times to give different thicknesses for the first gate dielectric layer. In a particular embodiment, a second gate dielectric layer may be formed over the first gate dielectric layer after etching the portion. The second gate dielectric layer can have a dielectric constant greater than the dielectric constant of the first gate dielectric layer. Subsequent gate electrode and source/drain region formation can be performed to form a transistor structure.

Method of forming an electronic device

A multiple gate oxidation process is provided. The process comprises the steps of (a) providing a silicon substrate () having a sacrificial oxide layer () thereon; (b) depositing and patterning a first layer of photoresist () on the sacrificial oxide layer, thereby forming a first region in which the sacrificial oxide layer is exposed; (c) etching the exposed sacrificial oxide layer within the first region, thereby forming a first etched region; (d) growing a first oxide layer () within the first etched region; (e) depositing and patterning a second layer of photoresist () on the sacrificial oxide layer and first oxide layer, thereby forming a second region in which the sacrificial oxide layer is exposed; (f) etching the exposed sacrificial oxide layer within the second region, thereby forming a second etched region; and (g) growing a second oxide layer () within the second etched region.

Integration of multiple gate dielectrics by surface protection

Embodiments of the present invention relate to semiconductor structures having multiple gate dielectric structures. One embodiment forms semiconductor devices in multiple regions having different dielectric thicknesses where the interface between the gate dielectric and the semiconductor substrate is protected to result in an improved (e.g. less rough) interface. One embodiment includes forming a dielectric layer overlying a substrate, partially etching the dielectric layer in at least one of the multiple regions, and ashing the dielectric layer. The remaining portion of the dielectric layer (due to the partial etch) may then help protect the underlying substrate from damage during a subsequent preclean. Afterwards, in one embodiment, the gate dielectric layer is grown to achieve a target gate dielectric thickness in at least one of the regions. This may also help further densify the gate dielectric layer. Processing may then be continued to form semiconductor devices in each of the multiple regions.

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Austin, TX, United States of America

Sangwoo Lim