Samsung Electronics Co., Ltd.

Sangoh Park

Hungbae Ahn

Seunghune Yang

Keunnam Kim

Dongjun Lee

Sunggon Jung

Jinho Lee

A pattern layout design method includes performing optical proximity correction (OPC) for a mask layout, thereby creating a corrected layout. Creation of the corrected layout includes creating a first corrected layout through grid snapping for an oblique edge of a mask layout designed on a grid layout, and performing optical proximity correction (OPC) for the first corrected layout, thereby creating a second corrected layout. Creation of the first corrected layout includes creating a first divisional point for the oblique edge or a residual edge, and shifting the first divisional point to one of four reference points adjacent to the first divisional point, thereby creating a first varied divisional point.

Method for designing pattern layout including oblique edges and method for manufacturing semiconductor device using the same

A semiconductor device may include a substrate including a cell region and a core/peripheral region. A plurality of bit line structures may be in the cell region of the substrate. A gate structure may be in the core/peripheral regions of the substrate. A lower contact plug and an upper contact plug may be between the bit line structures. The lower contact plug and the upper contact plug may be stacked in a vertical direction. A landing pad pattern may contact an upper sidewall of the upper contact plug. The landing pad pattern may be between an upper portion of the upper contact plug and an upper portion of one of the bit line structures. An upper surface of the landing pad pattern may be higher than an upper surface of each of the bit line structures. A peripheral contact plug may be formed in the core/peripheral regions of the substrate. A wiring may be electrically connected to an upper surface of the peripheral contact plug.

Methods of manufacturing semiconductor devices

A method of manufacturing a photomask set includes: preparing a mask layout, the mask layout including a plurality of first layout patterns apart from one another in a first region, wherein distances between center points of three first layout patterns adjacent to one another from among the plurality of first layout patterns respectively have different values; grouping pairs of first layout patterns, in which a distance between two first layout patterns adjacent to each other does not have a smallest value, and splitting the mask layout pattern into at least two mask layouts; and forming a photomask set including at least two photomasks each including a mask pattern corresponding to the first layout pattern included in each of the mask layout patterns split into at least two mask layouts.

Method of manufacturing photomask set for forming patterns

Semiconductor devices having landing pad patterns and methods of manufacturing the same

A method of manufacturing a mask may include identifying an error pattern of final patterns formed on a substrate, correcting a first target pattern on the basis of the error pattern, fracturing a first mask layout into a plurality of first segments on the basis of the corrected first target pattern, and correcting the first mask layout by biasing a plurality of first target segments corresponding to a first final target among the plurality of segments. The first mask layout may include a first extension pattern, final targets disposed in zigzags, and the first final target corresponding to the error pattern, and each of the plurality of first segments may corresponds to one of the final targets.

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Hwaseong-si, South Korea

Sangoh Park