Samsung Electronics Co., Ltd.

Sanghyeon Baeg

Amjad Z Qureshi

Edward H Yu

Scan chains to support debugging and manufacturing test modes for integrated circuit chips are made adaptable. Scan chains may be configured either in a multiple scan chain JTAG mode or in a multiple independent and parallel scan chain mode. The configuration transition between the scan modes is made by private instructions implemented in a JTAG controller, which supports the IEEE 1149.1 standard.

Adaptable scan chains for debugging and manufacturing test purposes

An integrated circuit includes a test port operating at a first clock speed and at least one functional logic block operating at a second clock speed which is faster than the first clock speed. A control register, formed by boundary scan cells, operates at the first clock speed and provides control inputs to the functional block to control emulation tasks. The control register is writable via a serial shift operation through the test port while the functional block is operating. The outputs of the control register which are being provided to the functional block are held constant during the serial shift operation. An observation register, formed by boundary scan cells, operates at the first clock speed, and is readable through the test port via a serial shift operation, while the functional block is operating. The observation register receives signals from the functional block indicating status of the functional block.

Low cost emulation scheme implemented via clock control using JTAG

In an integrated circuit, a clock to simulate the circuit's normal operation is generated from the JTAG clock input TCK.

Clock generation for testing of integrated circuits

JTAG test logic and a memory controller place an SDRAM in a self refresh mode prior to beginning JTAG testing. The memory controller can complete a current memory access and otherwise prepare for the JTAG test. During the JTAG test, self refresh mode operation of the SDRAM retains data without the need for a clock signal or refresh signals which are suspended for the JTAG test. Accordingly, after the JTAG test, circuit operation can continue without reinitializing data in the SDRAM.

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Cupertino, CA, United States of America

Sanghyeon Baeg