Samsung Electronics Co., Ltd.

Wisconsin Alumni Research Foundation

Snur & Db Foundation

Labgenomics Co., Ltd.

Sang-Joon Hwang

Kyo-Min Sohn

Ho-Young Song

Cheol Su Kim

Sung-Min Seo

Dong-hyun Sohn

Sang-Bo Lee

Nak-Won Heo

Yun-Young Lee

Seong-Jin Jang

Nam Sung Kim

Jung Ho Ahn

Chan-Kyung Kim

Young-Hoon Son

Myeong-O Kim

Seong-Il O

Je-Min Yu

Min-Soo Kim

Young-Sik Kim

Byung-Chul Kim

Jung-bae Lee

Dong-jin Lee

Young-Hyun Jun

Hyun-Jin Kim

Jun-hyung Kim

Woo-Jin Lee

Min-Sang Park

Ho-cheol Lee

Ho-young Song

Moon Il Kim

Won-Il Bae

Seung-Man Shin

Kyung-woo Kang

Hyun-Sung Shin

Youn-Sik Park

Ho-Seok Seol

Hyun Gyu Park

In-Su Choi

Tae-Yoon Lee

Kwang-II Park

Dae-Yeon Cho

Chi-Hwan Lee

Min-Ah Woo

Beom-seop Lee

Ho-Kyong Lee

Won-hwa Shin

Jung-Ho Jung

A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

Memory module, memory device, and processing device having a processor mode, and memory system

Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.

Device and method for repairing memory cell and memory system including the device

A semiconductor memory device includes a memory cell array, a repair control circuit and a refresh control circuit. The memory cell array includes a plurality of memory cells and a plurality of redundancy memory cells. The repair control circuit receives a repair command and performs a repair operation on a first defective memory cell among the plurality of memory cells during a repair mode. The semiconductor memory device may operate in a repair mode in response to the repair command. The refresh control circuit performs a refresh operation on non-defective ones of the plurality of memory cells during the repair mode.

Semiconductor memory devices including redundancy memory cells

A memory device may include a pre-charge control circuit, an active control circuit, and a driver circuit. The pre-charge control circuit may be configured to receive an active command after receiving a pre-charge command for a first bank, determine whether or not a pre-charge operation for the first bank has ended when receiving the active command, and generate an active instruction signal according to a result of the determination. The active control circuit may be configured to generate an active control signal for an active operation according to the active instruction signal. The driver circuit may be configured to control an active operation according to the active control signal.

Memory device, and memory system including the same

A semiconductor memory device includes a first memory block of a first type of memory; and a second memory block of a second type of memory having a different type from the first type. A first address region of the first memory block and a second address region of the second memory block are included in the same address domain. Each of the first and second memory blocks is accessed by an address signal including an address of the address domain, and the second memory block is a nonvolatile memory.

Semiconductor memory device and computer system including the same

Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.

Concentrated address detecting method of semiconductor device and concentrated address detecting circuit using the same

A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit.

Semiconductor memory device including sensing verification unit

Provided are a microorganism for use in quantification of homocysteine and methionine and a method of quantifying homocysteine and methionine in a sample by using the microorganism.

Microorganism for quantifying homocysteine, and use thereof

A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.

Semiconductor memory device for reducing ripple noise of back-bias voltage and method of driving semiconductor memory device

Growing community of inventors

Seoul, South Korea

Sang-Joon Hwang