Samsung Electronics Co., Ltd.

Sang-Jin Hyun

Hoon-Joo Na

Jae-Yeol Song

Wan-don Kim

Hong-bae Park

Sug-Hun Hong

Hye-Lan Lee

Hyung-Seok Hong

Hu-Yong Lee

Dong-Soo Lee

Chul-Sung Kim

Dong-Hyun Roh

Won-Keun Chung

Moon-Kyu Park

Yu-Gyun Shin

Jae-Jung Kim

Hyung-seok Hong

Hyeok-Jun Son

Hag-ju Cho

Jin-Kyu Jang

Yoon-Tae Hwang

Sung-Soo Kim

Min-Woo Song

Sang-Yong Kim

Oh-seong Kwon

Byoung-Hoon Lee

Sung-In Suh

Gyu-Hwan Ahn

Chan-Hyeong Lee

Ki-Joong Yoon

Jin-wook Lee

Sang-Bom Kang

Taek-Soo Jeon

Jeong-Hee Han

Do-Sun Lee

Dae-Young Kwak

Sung-kee Han

Joon-Gon Lee

Hoon-joo Na

Hong-Bae Park

Chae-Ho Na

Shigenobu Maeda

Si-Young Choi

Ki-Hyun Hwang

June-Hee Lee

Hyung-suk Jung

Hong-suk Kim

Seung-Jae Baik

Young-Moon Choi

Hyo-Seok Choi

Ryuji Tomita

Min-chan Gwak

Jong-Han Lee

Chang-Woo Sohn

Jeong-hyuk Yim

Ji-ye Kim

Jung-hwan Chun

Kuo Tai Huang

Seung-Jae Lee

Bo-un Yoon

Dong-Chan Kim

Yong-Ho Ha

Hyo-San Lee

Kun-Tack Lee

Ja-hum Ku

Ki-Hyung Ko

In-Sang Jeon

Jeong-Ik Kim

Sung-Kee Han

Kyung-Seok Oh

Kee-sang Kwon

Da-Il Eom

Do-hyun Lee

June-hee Lee

Soo-Jung Choi

Hye-Ian Lee

Hoon-ju Na

Hoon-joo Nah

Su-young Bae

Jun-Ki Park

Sung-woo Myung

Sun-gyu Choi

Young-suk Chai

A semiconductor device includes active fins on a substrate, a first isolation pattern on the substrate, the first isolation pattern extending on a lower sidewall of each of the active fins, a third isolation pattern including an upper portion extending into the first isolation pattern and a lower portion extending into an upper portion of the substrate, the lower portion contacting the upper portion of the third isolation pattern, and having a lower surface with a width greater than that of an upper surface thereof, and a second isolation pattern extending in the substrate under the third isolation pattern, contacting the third isolation pattern, and having a rounded lower surface.

Semiconductor devices

An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Method of forming an integrated circuit device having a contact capping layer

A semiconductor device includes a first transistor having a first threshold voltage, and including first channels, first source/drain layers connected to opposite sidewalls of the first channels, and a first gate structure surrounding the first channels and including a first gate insulation pattern, a first threshold voltage control pattern, and a first workfunction metal pattern sequentially stacked. The semiconductor device includes a second transistor having a second threshold voltage greater than the first threshold voltage, and including second channels, second source/drain layers connected to opposite sidewalls of the second channels, and a second gate structure surrounding the second channels and including a second gate insulation pattern, a second threshold voltage control pattern, and a second workfunction metal pattern sequentially stacked. A thickness of the second threshold voltage control pattern is equal to or less than a thickness of the first threshold voltage control pattern.

Integrated circuit device having fin-type active

A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

Semiconductor device

Semiconductor device having less defects in a gate insulating film and improved reliability and methods of forming the semiconductor devices are provided. The semiconductor devices may include a gate insulating film on a substrate and a gate electrode structure on the gate insulating film. The gate electrode structure may include a lower conductive film, a silicon oxide film, and an upper conductive film sequentially stacked on the gate insulating film. The lower conductive film may include a barrier metal layer.

Semiconductor devices and methods of fabricating the same

Provided are an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a semiconductor substrate; a device isolation layer defining an active region of the semiconductor substrate; a gate insulating layer on the active region; a gate stack on the gate insulating layer; a spacer on a sidewall of the gate stack; and an impurity region provided on both sides of the gate stack, wherein the gate stack includes a metal carbide layer and a metal layer on the metal carbide layer, wherein the metal carbide layer includes a layer having a carbon content of about 0.01 at % to about 15 at %.

Integrated circuit device and method of manufacturing the same

A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.

Methods of fabricating semiconductor devices using MOS transistors with nonuniform gate electrode structures

A semiconductor device may include active fins spaced apart from each other by a recess therebetween, each of the active fins protruding from an upper surface of a substrate, an isolation structure including a liner on a lower surface and a sidewall of a lower portion of the recess and a blocking pattern on the liner, the blocking pattern filling a remaining portion of the lower portion of the recess and including a nitride, a carbide or polysilicon, a gate electrode structure on the active fins and the isolation structure, and a source/drain layer on a portion of each of the active fins adjacent to the gate electrode structure.

Growing community of inventors

Suwon-si, South Korea

Sang-Jin Hyun