Freescale Semiconductor,inc.

Motorola Corporation

Sang-In Han

Pawitter Jit Mangat

Scott Daniel Hector

Kurt W Eisenbeiser

James R Wasson

Steven M Smith

Pawitter J S Mangat

Bing Lu

An EUV mask () includes an opening () that helps to attenuate and phase shift extreme ultraviolet radiation using a subtractive rather than additive method. A first embedded layer () and a second embedded layer () may be provided between a lower multilayer reflective stack () and an upper multilayer reflective stack () to ensure an appropriate and accurate depth of the opening (), while allowing for defect inspection of the EUV mask () and optional defect repair. An optional ARC layer () may be deposited in region () to reduce the amount of reflection within dark region (). Alternately, a single embedded layer of hafnium oxide, zirconium oxide, tantalum silicon oxide, tantalum oxide, or the like, may be used in place of embedded layers (). Optimal thicknesses and locations of the various layers are described.

Reflective mask useful for transferring a pattern using extreme ultra violet (EUV) radiation and method of making the same

Methods and apparatus are provided for extreme ultraviolet phase shift masks. The apparatus comprises a substrate, a reflectance region, and an attenuating phase shifter. The reflectance region overlies the substrate. The attenuating phase shifter overlies the reflectance region. The attenuating phase shifter includes a plurality of openings that expose portions of the reflectance region. The attenuating phase shifter attenuates radiation through a combination of absorption and destructive interference. The method comprises projecting radiation having a wavelength less than 40 nanometers towards a mask having a plurality of openings through an attenuating phase shifter. The plurality of openings expose a reflectance region in the mask. The attenuating phase shifter is less than 700 angstroms thick. Radiation impinging on the reflectance region exposed by said plurality of openings is reflected whereas radiation impinging on the attenuating phase shifter is attenuated and shifted in phase. The attenuating phase shifter attenuates using absorption and destructive interference.

Attenuated phase shift mask for extreme ultraviolet lithography and method therefore

An EUV mask () includes an opening () that helps to attenuate and phase shift extreme ultraviolet radiation using a subtractive rather than additive method. An etch stop layer () may be provided between a lower multilayer reflective stack () and an upper multilayer reflective stack () to ensure an appropriate and accurate depth of the opening. An absorber layer () may be deposited within the opening to sufficiently reduce the amount of reflection within dark region (). Optimal thicknesses and locations of the various layers are described.

Reflective mask useful for transferring a pattern using extreme ultraviolet (EUV) radiation and method of making the same

The present invention provides a method of fabricating a silicon fin useful in preparing FinFET type semiconductor structures. The method is particularly useful for creating fins with a width and smoothness appropriate for sub-50 nm type gates. The method begins with a silicon fin prepared by lithographic means from an SOI type structure such that the fin is larger in dimension, particularly width, than is desired in the final fin. If desired the silicon fin can include a nitride cap. A conformal diffusion layer, such as of silicon dioxide, is then deposited onto the fin and silicon dioxide substrate. A PECVD deposition using TEOS gas is one method to deposit the diffusion layer. The coated fin is then heated and exposed to oxygen. The oxygen diffuses through the diffusion layer and converts a portion of the silicon material to silicon dioxide. This oxidation continues until a desired amount of silicon material is converted to SiOsuch that the remaining silicon has the desired dimensions. The silicon fin is then exposed through wet etching steps that remove the silicon dioxide coating.

Method of fabricating three dimensional gate structure using oxygen diffusion

A pellicle membrane structure ( ) is made by a process that includes depositing ( ) a etch mask layer ( ) on the backside of the semiconductor wafer, deposting ( ) a first pellicle membrane protection layer ( ) on a frontside of the semiconductor wafer, depositing ( ) a layer of membrane material ( ) that is preferably SiOF on the first membrane protection layer, and depositing ( ) a second pellicle membrane protection layer ( ) on the membrane material layer, forming a pattern ( ) for an opening ( ) in the semiconductor, and etching ( ) to form the opening. Oxygen plasma ( ) is then used to remove carbon from the exposed portions of the pellicle membrane protection layers, which are preferably SiCN, which in the preferable embodiment changes the exposed surfaces to SiOF, thereby forming a thin SiOF membrane ( ) over the opening.

Structure and process for a pellicle membrane for 157 nanometer lithography

A desired pattern is formed in a photoresist layer that overlies a semiconductor wafer using a reflective mask. This mask is formed by consecutively depositing a reflective layer, an absorber layer and an anti-reflective (ARC) layer. The ARC layer is patterned according to the desired pattern. The ARC layer is inspected to find areas in which the desired pattern is not achieved. The ARC layer is then repaired to achieve the desired pattern with the absorber layer protecting the reflective layer. The desired pattern is transferred to the absorber layer to reveal the reflective portion of mask. Radiation is reflected off the reflective mask to the semiconductor wafer to expose the photoresist layer overlying the semiconductor wafer with the desired pattern.

Method of making an integrated circuit using a reflective mask

A desirable pattern is formed in a photoresist layer that overlies a semiconductor wafer using an attenuating phase shift reflective mask. This mask is formed by consecutively depositing an attenuating phase shift layer, a buffer layer and a repairable layer. The repairable layer is patterned according to the desirable pattern. The repairable layer is inspected to find areas in which the desirable pattern is not achieved. The repairable layer is then repaired to achieve the desirable pattern with the buffer layer protecting the attenuating phase shift layer. The desirable pattern is transferred to the buffer layer and then transferred to the attenuating phase shift layer to achieve the attenuating phase shift reflective mask. Radiation is reflected off the attenuating phase shift reflective mask to the photoresist layer to expose it with the desirable pattern.

Method of forming a pattern on a semiconductor wafer using an attenuated phase shifting reflective mask

A method and apparatus for determining stress levels of membrane masks that may be used in membrane-based lithographic techniques is presented. A piezoelectric plate ( ) is used to induce vibrations into the membrane mask ( ), where the frequency and amplitude of the vibrations induced in the membrane layer ( ) are optically sensed. By comparing the stimulus applied to the piezoelectric plate ( ) with the response sensed optically in a gain phase analyzer ( ), a frequency graph ( ) associated with the membrane layer ( ) is constructed such that resonant frequencies are easily determined. These resonant frequencies can then be used to calculate the stress associated with the membrane layer ( ).

Growing community of inventors

Phoenix, AZ, United States of America

Sang-In Han