Skhynix Inc.

Korea Advanced Institute of Science and Technology

Samsung Electronics Co., Ltd.

Kolon Industries, Inc.

Sang Hwan Kim

Yoo Jin Lee

Koeng Su Lim

Jin Koog Shin

Sang Il Park

Seong Won Kwon

Ji Hwan Yang

Joong Hwan Kwak

Ki Yong Lee

Jong Hyun Kim

Min Sung Kim

Min Su Kim

Kyeong Min Chae

Hyung Ju Choi

Jae Ryoung Lee

A memory device, and a method of operating the same, includes a plurality of pages, a peripheral circuit, and control logic. The peripheral circuit is configured to receive a command, an address, and data from an external controller to program a page selected from among the plurality of pages, and to generate internal input data depending on an input mode for the command, the address, and the data. The control logic is configured to determine whether internal input data is to be generated based on the data depending on the input mode and to control the peripheral circuit so that a program operation of programming the internal input data is performed.

Memory device and method of operating with different input/output modes

A memory device includes a first pad, a second pad, and a double data rate (DDR) test controller. The first pad may receive a write enable signal. The second pad may receive a data strobe signal. The DDR test controller is connected to the first pad and the second pad and outputs an internal write enable signal and an internal data strobe signal. The DDR test controller generates the internal data strobe signal based on the write enable signal received through the first pad, in at least a portion of a DDR test operation of the memory device.

Memory device

A chip ejecting apparatus includes a table configured to be provided with a dicing tape and a target chip adhered to an upper surface of the dicing tape, an ejector unit including a plurality of gas holes configured to inject a gas toward a lower surface of the dicing tape, and a control unit configured to separately control on/off operations of the plurality of gas holes and select an active gas hole group from the plurality of gas holes. The active gas hole group is selected to overlap the target chip, and is configured to inject the gas toward the dicing tape along a direction from a first edge of the target chip toward a second edge of the target chip opposite to the first edge of the target chip.

Chip ejecting apparatus

A semiconductor memory device includes a memory cell array, a buffer unit, control logic, and a decoding circuit. The memory cell array includes a plurality of memory cells. The buffer coupled to the memory cell array, and includes a first memory area, a second memory area, and a conversion memory area. The control logic outputs a mode control signal representing an operating mode of the buffer. The decoding circuit controls the operating mode of the buffer such that the conversion memory area operates as any one of a main memory area and a repair memory area, based on the mode control signal.

Decoding circuit to select a column select line corresponding to an address signal and semiconductor memory device having the same

The present disclosure relates to a memory device and a memory system having the same. The memory device includes page buffers arranged in a first direction and a second direction perpendicular to the first direction, a first storage group and a second storage group arranged adjacent to the page buffers in the second direction, and a switch circuit arranged between the first storage group and the second storage group and selectively coupling the first storage group and the second storage group to data lines according to a number of page buffers and a number of first and second storage groups.

Memory device and memory system having the same

A semiconductor package includes a package substrate and semiconductor chips stacked on the package substrate. The package substrate may include at least one first chip enablement finger, at least one second chip enablement finger, and a chip enablement pad selection finger. Each of the semiconductor chips includes a first chip enablement pad connected to the at least one first chip enablement finger, a second chip enablement pad connected to the at least one second chip enablement finger, and a chip enablement pad selection pad connected to the chip enablement pad selection finger. The first chip enablement pads of the semiconductor chips or the second chip enablement pads of the semiconductor chips are optionally activated by a signal applied to the chip enablement pad selection finger.

Semiconductor packages including chip enablement pads

A semiconductor apparatus includes a controller configured to generate a plurality of control signals for selecting an operation mode of the semiconductor apparatus in response to a number of input chip enable pulses, and an output driving unit configured to be operated according to the operation mode of the semiconductor apparatus based on the plurality of control signals.

Semiconductor apparatus and semiconductor system

A semiconductor stacked package may include a substrate formed with a plurality of coupling pads, a plurality of semiconductor chips stacked on the substrate. The semiconductor stacked package may also include first circuit units disposed on each of the semiconductor chips, and electrically connected with the coupling pads by the medium of bonding pads. The semiconductor stacked package may include second circuit units disposed on each of the semiconductor chips and electrically disconnected with the coupling pads, connection pads disposed on each of the semiconductor chips and corresponding to the second circuit units, and blocking circuits coupled between the second circuit units and the connection pads. The semiconductor stacked package may also include bonding wires electrically connecting the bonding pads and the coupling pads.

Semiconductor stacked package

Provided is a method of manufacturing a see-through-type integrated solar cell and a method of manufacturing the same. The method comprises forming a first conductive material being apart and strip patterned on a transparent substrate so that the first conductive material comprises a predetermined space for enabling light to directly pass through the transparent substrate, forming a solar cell (semiconductor) layer, obliquely depositing a second conductive material and etching the solar cell layer using the second conductive material layer as a mask.

See-through-type integrated thin-film solar cell, method of manufacturing the same and method of electrically series connecting unit cells thereof

Provided are an integrated thin-film solar cell and a method of manufacturing the same. The method comprises forming and patterning a conductive material to be adjacently spaced a predetermined distance apart from each other on a substrate; forming a solar cell (semiconductor) layer on the resultant substrate; obliquely depositing a first transparent conductive material on the solar cell layer; etching the solar cell layer using the first transparent conductive material as a mask; and obliquely depositing a second transparent conductive material on the resultant substrate, and electrically connecting the conductive material with the first transparent conductive material.

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Seoul, South Korea

Sang Hwan Kim