Stats Chippac Pte. Ltd.

Sang-Ho Lee

Soo-San Park

Jong-Woo Ha

DaeSik Choi

Taewoo Lee

BumJoon Hong

Hyeog Chan Kwon

Jong Wook Ju

DongSoo Moon

SeungYun Ahn

SooMoon Park

Byung Tai Do

DongSam Park

SeungYong Chai

Hyunjoo Kim

BoHan Yoon

Changyong Lee

YoungSik Cho

Hunki Lee

A stacked integrated circuit package system is provided forming a first molded chip comprises attaching a conductor on a wafer, applying an encapsulant around the conductor, and exposing a surface of the conductor in the encapsulant, attaching a first electrical interconnect on the conductor of the first molded chip and stacking an integrated circuit device on the first molded chip with an electrical connector of the integrated circuit device connected to the conductor of the first molded chip with the first electrical interconnect.

Stacked integrated circuit package system with face to face stack configuration

An integrated circuit packaging system is provided including: a first device having a first backside and a first active side; and a waferscale spacer having an exact fit at all four corners adjacent to an edge of the first device and a recess along the edge of the first device.

Integrated circuit package system with waferscale spacer

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a package stack assembly, having a contact pad, on the base substrate; applying an encapsulation having a cavity with a tapered side directly over the package stack assembly, the contact pad exposed in the cavity; attaching a recessed circuitry unit in the cavity and on the contact pad, a chamber of the cavity formed by the recessed circuitry unit and the tapered side of the cavity; and mounting a thermal structure over the recessed circuitry unit, the cavity, and the encapsulation.

Integrated circuit packaging system with thermal dispersal structures and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold chase having a hole; and forming an encapsulation through the dispense port or the hole, the encapsulation surrounding the integrated circuit including completely filled in a space between the integrated circuit and the package carrier, and in a portion of the hole, the encapsulation having an elevated portion or a removal surface resulting from the elevated portion detached.

Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereof

A method of operation of a workpiece displacement system includes: providing a head including a conduit, a recess port, and a channel, the conduit configured such that its major axis intersects the recess port and the channel; inserting a force distribution member into the recess port; and supplying a negative pressure state through the head and the force distribution member.

Workpiece displacement system

An integrated circuit packaging system with ultra-thin die is provided including providing an ultra-thin integrated circuit stack, having a vertical sidewall contact, including providing a semiconductor wafer having an active side, forming a solder bump on the active side of the semiconductor wafer, forming a support layer over the solder bump and the active side of the semiconductor wafer, forming an ultra-thin wafer from the semiconductor wafer and singulating the ultra-thin integrated circuit stack for exposing the vertical sidewall contact, mounting the ultra-thin integrated circuit stack on a substrate, and coupling the substrate to the vertical sidewall contact.

Integrated circuit packaging system with ultra-thin die

An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.

Integrated circuit package system with stackable devices and a method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; depositing a through-conductor on the base substrate; depositing a semiconducting layer on the base substrate and around the through-conductor; forming a metal trace connected to the through-conductor; depositing a dielectric surrounding the metal trace; and removing the base substrate.

Integrated circuit packaging system with multi-stacked flip chips and method of manufacture thereof

A method of manufacture of an integrated circuit packaging system includes: mounting a substrate-less integrated circuit package, having a terminal having characteristics of an intermetallic compound, over a substrate; connecting the substrate and the substrate-less integrated circuit package; and forming a base encapsulation over the substrate-less integrated circuit package with the terminal exposed.

Integrated circuit packaging system with cavity and method of manufacture thereof

A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect.

Integrated circuit package system employing an offset stacked configuration and method for manufacturing thereof

A method for manufacturing a package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit die connected thereto; forming an encapsulant between the interposer substrate and the base substrate, the encapsulant encapsulating the first integrated circuit die; and forming a via z-interconnection extending through the encapsulant and one of the substrates to the other of the substrates.

Package-on-package system with via z-interconnections and method for manufacturing thereof

An integrated circuit packaging system is provided including forming a first device wafer having a first backside and a first active side; forming a waferscale spacer wafer having a waferscale spacer and a first opening; mounting the waferscale spacer wafer on the first backside; and singulating an first integrated circuit die having the waferscale spacer from the first device wafer having the first backside with the waferscale spacer wafer thereon.

Integrated circuit package system for stackable devices

An integrated circuit package system includes: providing a substrate; attaching a base die to the substrate, the base die having a relief region with a shaped cross-section; and connecting a bond wire between an active base surface of the base die and the substrate, the bond wire extending through the shaped cross-section of the relief region.

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Yeoju, South Korea

Sang-Ho Lee