Tokyo Electron Limited

Sang Cheol Han

Soo Doo Chae

Sunghil Lee

Alok Ranjan

Sergey Alexandrovich Voronin

Youngwoo Park

Yusuke Yoshida

Christopher Talone

Shyam Sridhar

Christopher Catano

Iljung Park

Technologies for fabricating a vertical dynamic random access memory (DRAM) structure include forming a DRAM cell hole through a word line layer and an associated substrate such that a first section of the DRAM cell hole extends through the word line layer and a second section of the DRAM cell hole extends through the substrate in vertical alignment with the first section. A pillar capacitor structure is initially formed using the second section of the DRAM cell hole, followed by the formation of a transistor using the first section of the DRAM cell hole as a channel for the transistor. Due to the use of a common DRAM cell hole, the pillar capacitor structure and the channel are in vertical alignment. The substrate is subsequently flipped and removed from the pillar capacitor structure, which is further processed to form a pillar capacitor. In some embodiments, the channel may be formed from a deposition of indium gallium zinc oxide (IGZO).

Technologies for fabricating a vertical DRAM structure

A three-dimensional (3D) memory structure includes a memory array formed on a side of a substrate, a far-back-end-of-line (FBEOL) structure formed on the memory array, and a back-end-of-line (BEOL) structure formed on another side of the substrate opposite the side on which the memory array and the BEOL structure are formed. Methodologies to fabricate the 3D memory structure are also disclosed and include forming the memory array on the substrate, forming the FBEOL on the memory array, flipping the substrate, and forming the BEOL on the opposite side of the substrate. Alternative 3D memory structures and fabrication methodologies are also disclosed.

Technologies for fabricating a 3D memory structure

Residue at the base of a feature in a substrate to be etched is limited so that improved profiles may be obtained when forming vertical, narrow pitch, high aspect ratio features, for example fin field effect transistor (FinFET) gates. A thin bottom layer of the feature is formed of a different material than the main layer of the feature. The bottom material may be comprised of a material that preferentially etches and/or preferentially oxidizes as compared to the main layer. The bottom layer may comprise silicon germanium. The preferential etching characteristics may provide a process in which un-etched residuals do not remain. Even if residuals remain, after etch of the feature, an oxidation process may be performed. Enhanced oxidation rates of the bottom material allow any remaining residual to be oxidized. Plasma oxidation may be used. The oxidized material may then be removed by utilizing standard oxide removal mechanisms.

Method for gate stack formation and etching

Embodiments provide raised pad formations for step contacts in three-dimensional structures formed on microelectronic workpieces. Steps are formed in a multilayer stack that is used for the three-dimensional structure. The multilayer stack includes alternating non-conductive and conductive layers. For one embodiment, alternating oxide and polysilicon layers are used. The steps expose contact regions on different conductive layers. Material layers are formed on the contact regions to form raised pads. The material layers preferably have a high selectivity with respect to the non-conductive material for etch processes. A protective layer is formed over the steps and the raised pads, and contact holes are formed through the protective layer to the raised pads. Contacts are then formed within the contact holes. The raised pads inhibit punch-through of the non-conductive layers during the forming of the contact holes thereby improving performance of resulting devices formed in the microelectronic workpieces.

Raised pad formations for contacts in three-dimensional structures on microelectronic workpieces

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Sang Cheol Han