Cadence Design Systems, Inc.

Sandeep Pagey

Frank Armbruster

Bijaya Kumar Sahu

Yaron Peri-Glass

Swapnajit Chakraborti

Hannes Froehlich

Boris Gommershtadt

Yael Duek-Golan

Alok Jain

Axel Siegfried Scherer

Abhishek Kanungo

Dan Leibovich

Anuja Jain

F Erich Marschner

Christer Cederberg

The present disclosure relates to a method for verifying a digital design using a computing device. The method may include determining one or more tests associated with verifying the digital design and generating, using the computing device, a verification result by performing one or more verification runs on the digital design. The method may further include merging coverage data generated by the one or more verification runs and ranking the one or more tests based upon, at least in part, a first verification run having a first configuration and a second verification run having a second configuration, wherein the first and second configurations differ.

Ranking process for simulation-based functional verification

In one embodiment of the invention, a method for verification of an integrated circuit design is disclosed. The method includes independently executing simulation runs in response to a plurality of coverage models to respectively generate a plurality of coverage data for a plurality of functional blocks within one or more integrated circuit designs; generating a target coverage model to selectively merge at least first coverage data associated with a first coverage model and second coverage data associated with a second coverage model; and in response to the target coverage model and the plurality of simulation runs, selectively projecting the plurality of coverage data into a merged coverage data result associated with the target coverage model. The method may further store the merged coverage data results into a storage device. The plurality of simulation runs may include at least one functional simulation run and at least one formal verification run.

Configuration-based merging of coverage data results for functional verification of integrated circuits

An improved method, system, user interface, and computer program product is disclosed for performing graphical analysis of coverage. According to some approaches, a graphical user interface uses treemaps to provide analysis of verification coverage. This allows the user to efficiently obtain the overall and/or complete picture of the coverage space, as well as the relative size of nodes in terms of number of coverage elements contained in them. Moreover, the present treemap approach provides relative comparison of coverage of the nodes and allows the user to identify whether there is any missing coverage, and if so, whether the missing coverage evenly balanced. This information is very useful for the decision made by the user regarding overall coverage and steps to be taken to improve the coverage.

Method and system for implementing graphical analysis of hierarchical coverage information using treemaps

A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.

Verification plans to merging design verification metrics

In some embodiments of the invention, a method and apparatus of consolidating all types of coverage metrics, obtained from an HDL simulator, under a single common framework is described. In other embodiments of the invention, a method and an apparatus are disclosed for performing ranking from a verification plan using total coverage metric.

Systems for total coverage analysis and ranking of circuit designs

A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment, design and verification checksums are calculated for instances of a desired module. The design and verification checksums may be used to further derive hierarchical design and functional checksums. In another embodiment, these checksums are used to merge multiple databases produced by verification runs. In a further embodiment a computing apparatus is provided. The computing apparatus is configured to merge multiple verification databases.

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Noida, India

Sandeep Pagey