Intel Corporation

Sandeep Ahuja

Robin A Steinbrecher

David Shia

Phil Geng

Jeffory L Smalley

Ralph V Miele

Susan F Smith

Michael Berktold

Krishnakanth Venkata Sistla

Rajat Agarwal

Ioan Sauciuc

Tessil Thomas

Casey R Winkel

Eric W Buddrius

Timothy Y Kam

Barrett M Faneuf

David J Ayers

Phani Kumar Kandula

Kenan Huseyin Arik

David Richardson

Marc Milobinski

Mengqi Liu

Aaron P Anderson

Carlos Alvizo Flores

Brendan T Pavelek

Fernando Gonzalez Lenero

Roger D Flynn

Howard Chin

Minh T D Le

Jeremy Ridge

Avinash Sodani

Ankush Varma

Vivek Garg

Je-Young Chang

Vasudevan Srinivasan

Ashish Gupta

Xiaoning Ye

Jin Yang

Nikhil Gupta

Nishi Ahuja

Eric Dwight McAfee

Chris Poirier

Meenakshisundaram Chinthamani

Neal E Ulen

Timothy Glen Hanna

Shrenik Kothari

Jimmy Chuang

Andres Ramirez Macias

Jorge Contreras Perez

Eric D Mcafee

Gilberto Rayas Paredes

Martin Mark T Rowland

Francisco Gabriel Lozano Sanchez

Maria De La Luz Belmont Velazquez

Jacob Mcmillian

Jinho Suh

Robin Steinbrecher

An apparatus is described. The apparatus includes a bolster plate having a first fixturing element and a strap. The strap is positioned along a frame arm of the bolster plate. The strap has a second fixturing element to be fixed to a cooling mass. The strap is to diminish movement of the cooling mass along the frame arm's dimension and a dimension that is orthogonal to the frame arm's dimension. A semiconductor chip package is to be placed in a window opening formed by the bolster plate's frame arms. The cooling mass is to be thermally coupled to the semiconductor chip package.

Cooling assembly with strap element to diminish lateral movement of cooling mass during installation of the cooling mass

Techniques for processor loading mechanisms are disclosed. In the illustrative embodiment, a heat sink is in contact with a top surface of a processor, applying a downward force on the processor. A load plate is also in contact with the processor, applying a downward force to the processor as well. The combination of the downward force from the load plate and the heat sink keep the processor in good physical contact with pins of the processor socket. The heat sink has enough force applied to the processor to be in good thermal contact with the processor without applying higher stress to the heat sink. The load plate can apply force to the processor without regard to the thermal characteristics of the load plate. Other embodiments are envisioned and described.

Technologies for processor loading mechanisms

An apparatus is described. The apparatus includes a semiconductor chip package loading assembly having a heat sink and a first magnetic material, the first magnetic material to be mechanically coupled to a first side of a printed circuit board that is opposite a second side of the printed circuit board where input/outputs (I/Os) of the semiconductor chip package interface with the printed circuit board. The first magnetic material to be positioned between the printed circuit board and a second magnetic material. The first magnetic material is to be magnetically attracted to the second magnetic material to impede movement of the heat sink.

Magnetically secured semiconductor chip package loading assembly

An apparatus is described. The apparatus includes a ceiling part and a floor part of a thermally conductive component to be placed upon a semiconductor chip package integrated heat spreader to remove heat from at least one semiconductor chip within the semiconductor chip package. Respective inner surfaces of the floor part and the ceiling part are to face one another with space in between such that one or more cavities exist within the thermally conductive component between the respective inner surfaces. The apparatus includes a frame component to be abutted against at least one of the ceiling part and the floor part to impede deformation of at least one of the ceiling part and the floor part when loading forces are applied to a thermal assembly that includes the thermally conductive component and the semiconductor chip package.

Thermally conductive chamber with stiffening structure for thermal cooling assembly of semiconductor chip package under high loading force

An apparatus is described. The apparatus includes a housing including a base and sidewalls. The housing is to support a circuit board. The apparatus also includes a heat sink to be supported by the housing independent of the circuit board. The heat sink is to be thermally coupled to a semiconductor package attached to the circuit board. The heat sink is to be closer to the base of the housing than the circuit board is to be to the base of the housing.

Electronic systems with inverted circuit board with heat sink to chassis attachment

An apparatus is described. The apparatus includes an electronic system. The electronic system includes a chassis. The electronic system includes a semiconductor chip cooling component that is rigidly fixed to the chassis. The electronic system includes a packaged semiconductor chip having a lid that is contact with the semiconductor chip cooling component. The electronic system includes an electronic circuit board. The packaged semiconductor chip is electro-mechanically attached to the electronic circuit board.

In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.

Apparatus and method to provide a thermal parameter report for a multi-chip package

An apparatus incorporating a multi-surface heat sink may comprise an integrated circuit die, a heat spreader, a plate element, and a heat sink. The heat spreader may be positioned above the IC die. The plate element may be positioned above the heat spreader. A bottom surface of the heat sink may have a first region positioned above the plate element. One or more spring elements may be positioned between the plate element and the first region of the bottom surface of the heat sink. The one or more spring elements may be under a compressive load between the plate element and the heat sink. One or more thermal conduit elements may be secured to both the plate element and the heat sink. The one or more thermal conduit elements may apply at least a part of the compressive load between the plate element and the heat sink.

Multi-surface heat sink suitable for multi-chip packages

In one embodiment, a processor includes a non-volatile storage to store a plurality of configurations for the processor, the non-volatile storage including a plurality of entries to store configuration information for the processor for one of the plurality of configurations, the configuration information including at least one of a guaranteed operating frequency and a core count, at least one of the entries to store the core count. The processor further includes a power controller to control the processor to operate at one of the plurality of configurations based at least in part on a selected thermal set point of a plurality of thermal set points of the processor, each of the plurality of thermal set points associated with one of the configurations. Other embodiments are described and claimed.

System, apparatus and method for controllable processor configuration based on a temperature specification

In one embodiment, a processor comprises: a first die including at least one core and at least one first die thermal sensor; a second die including at least one memory and at least one second die thermal sensor; and a thermal controller to receive first thermal data from the at least one first die thermal sensor and second thermal data from the at least one second die thermal sensor, calculate a first thermal margin for the first die based at least in part on the first thermal data and a first thermal loadline for the first die and calculate a second thermal margin for the second die based at least in part on the second thermal data and a second thermal loadline for the second die. Other embodiments are described and claimed.

Determining thermal margins in a multi-die processor

A method for determining whether to perform maintenance for an electronic device includes generating a baseline characterization of thermal performance for a heat-generating component of the electronic device at a baseline date. The method also includes generating an assessment characterization of the thermal performance at an assessment date after the baseline date. The method further includes generating a historical trend that includes the baseline characterization and the assessment characterization. Additionally, the method includes determining whether to perform maintenance for the heat-generating component based on the historical trend and a specified maintenance parameter.

Maintenance prediction of electronic devices using periodic thermal evaluation

Disclosed herein is a computing device configured to implement thermal throttling of a component of the computing device. The computing device includes an electronic component and a temperature sensor thermally coupled to the electronic component. The computing device also includes a thermal management controller to receive a temperature measurement from the temperature sensor and generate a throttling factor for the electronic component. If the temperature measurement is greater than a specified threshold, the throttling factor is to reduce performance of the electronic component to be at least the performance guarantee for the electronic component.

Thermal throttling of electronic devices

Methods and systems may provide for identifying a thermal management setting in a computing system, and comparing the thermal management setting to valid configuration information. In addition, the thermal management setting may be modified if it does not comply with the valid configuration information, wherein the modification can cause the thermal management setting to comply with the valid configuration information. Additionally, a threat risk notification can be initiated in order to notify users of the non-compliance.

Securing thermal management parameters in firmware from cyber attack

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University Place, WA, United States of America

Sandeep Ahuja